|
Core Specifics |
| Supported Device Family |
AMD Versal™
adaptive SoC |
| Supported User Interfaces |
Native, AXI4-Stream, AXI4,
AXI4-Lite
|
| Provided with
Core
|
| Design Files |
System Verilog RTL |
| Example Design |
N/A |
| Test Bench |
N/A |
| Constraints File |
XDC |
| Simulation Model |
N/A |
| Supported S/W Driver |
N/A |
| Tested Design
Flows |
| Design Entry |
Vivado Design Suite
|
| Simulation |
For supported simulators, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973). |
| Synthesis |
Vivado Synthesis |
| Support |
| All Vivado IP Change
Logs |
Master Vivado IP Change Logs:
72775
|
|
Support web
page
|
- For a complete list of supported devices, see the AMD Vivado™
IP catalog.
- The Embedded FIFO Generator core
supports the UniSim simulation model.
- For the supported versions of the tools, see
the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973).
|