AXI FIFO Feature Summary - 1.0 English

AXI FIFO Feature Summary - 1.0 English - PG327

Embedded FIFO Generator LogiCORE IP Product Guide (PG327)

Document ID

PG327

Release Date

2023-05-16

Version

1.0 English

The following table summarizes the supported Embedded FIFO Generator core features for each clock configuration and memory type.

Table 1. AXI FIFO Configuration Summary
FIFO Options	Common Clock		Independent Clock
FIFO Options	Block RAM/UltraRAM	Distributed Memory	Block RAM	Distributed Memory
Full¹	✓	✓	✓	✓
Programmable Full²	✓	✓	✓	✓
Empty	✓	✓	✓	✓
Programmable Empty²	✓	✓	✓	✓
Data Counts	✓	✓	✓	✓
ECC	✓		✓
Mapped to s_axis_tready/s_axi_awready/s_axi_wready/m_axi_bready/s_axi_arready/m_axi_rready depending on the Handshake Flag Options in the IDE. Mapped to m_axis_tvalid/m_axi_awvalid/m_axi_wvalid/s_axi_bvalid/m_axi_arvalid/s_axi_rvalid depending on the Handshake Flag Options in the IDE.Provided as sideband signal depending on the IDE option.Mapped to s_axis_tready/s_axi_awready/s_axi_wready/m_axi_bready/s_axi_arready/m_axi_rready depending on the Handshake Flag Options in the IDE.