System Considerations - 1.2 English - PG325

Multi-Scaler LogiCORE IP Product Guide (PG325)

Document ID
PG325
Release Date
2025-12-03
Version
1.2 English

The Video Multi-Scaler IP must be configured to operate properly. There must be sufficient bandwidth available for this IP to function properly.

  • The bandwidth needed (in MB/s) for a memory layer can be calculated with the following equation: 6.105 B a n d w i d t h   M B / s   =   f p s   ×   h e i g h t   ×   s t r i d e

    Where, 'fps' is the number of frames per second the Video Multi-Scaler is operating, 'height' is the height in lines of the image, and 'stride' is the stride in bytes of the image.

    For example, for a 2 output 3840x2160@30 RGB 8-bit input and output video, the bandwidth requirement is calculated as follows:

    S1 (Source Bandwidth for out1) = 30 x 2160 x 3840 x 3 = 712 MB/s

    D1 (Destination Bandwidth for out1) = 30 x 2160 x 3840 x 3 = 712 MB/s

    T1 (Total bandwidth of out1) = S1 + D1 = 1.39 GB/s

    T (Total bandwidth of the system, that is, for 2 outs) = 2 x T1 = 2.78 GB/s

  • The clock required to achieve the performance is calculated as follows:

    Number of pixels operated for an Output = max(input width, output width) x max(input height, output height) x frame rate

    Number of pixels operated by all Outputs: Pix_total = Summation of number of pixels operated for an output

    Minimum clock required to achieve the performance = Pix_total/Samples per clock

    The actual clock in design needs to be approximately 10% higher than the minimum clock requirement.