Synthesizable Example Design - Synthesizable Example Design - 1.2 English

Synthesizable Example Design - Synthesizable Example Design - 1.2 English - PG325

Multi-Scaler LogiCORE IP Product Guide (PG325)

Document_ID

PG325

Release_Date

2026-07-22

Version

1.2 English

The synthesizable design uses the Zynq UltraScale+ MPSoC microprocessor as the AXI4 master. The interrupt port of the Multi-Scaler connects to the Zynq UltraScale+ MPSoC. The Multi-Scaler sends the interrupt after generating all the outputs.

Figure 1. Example Design

The synthesizable example design requires both AMD Vivado™ and AMD Vitis™ tools.

The first step is to run synthesis, implementation and bitstream generation in Vivado. After all those steps are done, select File > Export > Export Hardware.

In the window, select Include bitstream, select an export directory, and click OK.

The remaining work is performed in the Vitis tool. The Video Multi-Scaler example design file can be found in the following Vitis directory: <install_directory>/<release>/data/embeddedsw/XilinxProcessorIPLib/drivers/v_multi_scaler_v1_2/examples/.

The example application design source files (contained within examples folder) are tightlycoupled with the v_multi_scaler example design available in Vivado IP catalog. The vmulti_scaler_example.tcl automates the process of generating the downloadable bit and .elf files from the provided example .hdl file.