The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 12/03/2025 Version 1.2 | |
| Features | Updated topic. |
| Interface | Updated screenshot, and added new parameter. |
| User Parameters | Added new parameter. |
| 12/20/2023 Version 1.2 | |
| Registers Description | Height In and Out 0 description corrected/updated to be the same as it is in the table. |
| 10/19/2022 Version 1.2 | |
| System Considerations | Added bandwidth and clock calculations. |
| 04/27/2022 Version 1.2 | |
| Register Space | Updated register names in Table 20. |
| Registers Description | Updated Control Register. |
| 08/09/2021 Version 1.2 | |
| Example Design | Added VCK190. |
| Prerequisites | Added topic. |
| 02/04/2021 Version 1.2 | |
| Features | Updated spatial resolutions value. |
| Performance | Added support for AMD Versal™ ACAP. |
| Common Interface Signals | Updated ap_rst_n description. |
| Memory Mapped AXI4 Interface | Added Bits[31:30] information in Y10 Pixel Format. |
| Register Space |
|
| User Parameters | Updated default value of HSC_MAX_WIDTH. |
| Customizing and Generating the Core | Updated Main Configuration Tab figure. |
| Example Design | Added ZCU104. |
| Synthesizable Example Design | Updated Vitis directory. |
| Create the ELF in the Vitis Tools | Updated procedure and figures. |
| Verification, Compliance, and Interoperability | Added Vitis and removed Vivado for simulation. |
| Upgrading in the Vivado Design Suite | Added upgrade information. |
| 07/08/2020 Version 1.0 | |
| Example Design | Added table for supported platforms. |
| 12/11/2019 Version 1.0 | |
| Synthesizable Example Design |
|
| 06/18/2019 Version 1.0 | |
| Features | Updated. |
| Registers Description | Updated. |
| Accessing 64-bit DDR Memory Location | Added new section. |
| 12/5/2018 Version 1.0 | |
| Initial release. | N/A |