- Control (0x00000) Register
- Controls the operation of the core. Bit[0] of the Control register,
ap_start, kicks off the core from software. Writing 1 to this bit, starts the core to generate a video frame. Bit[1] of the Control register,ap_done, indicates when the IP has completed all operations in the current transaction. A logic 1 on this signal indicates that the IP has completed all operations in this transaction.Bit[2] of the Control register,
ap_idle, signal indicates if the IP is operating or idle (no operation). The idle state is indicated by logic 1. This signal is asserted low after the IP starts operating. This signal is asserted high when the IP completes operation and no further operations are performedBit[3] of the Control register,
ap_ready, signal indicates when the IP is ready for new inputs. It is set to logic 1 when the IP is ready to accept new inputs, indicating that all input reads for this transaction are completed. If the IP has no operations in the pipeline, new reads are not performed until the next transaction starts. This signal is used to make a decision on when to apply new values to the input ports and whether to start a new transactionBit[5] of the Control register, is for flushing pending AXI transactions. This bit must be set and held (until reset) by software to flush pending transactions. When this is set, the hardware is expecting a hard reset.
Bit[6] of the Control register is the flush status bit and is asserted when the flush is done. Bit[7] of the Control register,
auto_restart, can be set to enable the auto-restart mode. Thereafter, the IP restarts automatically at the end of each transaction. - Global Interrupt Enable (0x00004) Register
- Master control for all interrupts. Bit[0] enables/disables all core interrupts.
- IP Interrupt Enable (0x00008) Register
- Allows you to enable interrupts selectively. Currently, two interrupt
sources are available
ap_doneandap_ready.ap_donetriggers after the frame processing is complete, whileap_readytriggers after the core is ready to start processing the next frame. - IP Interrupt Status (0x0000C) Register
- Dual-purpose register. When an interrupt occurs, the corresponding interrupt source bit is set in this register. In readback mode (Get status), the interrupting source can be determined. In writeback mode (Clear interrupt), the requested interrupt source bit is cleared.
- IP Number of Outs (0x00010) Register
- Allows you to configure the number of outputs generated by the IP. To avoid processing errors, restrict values written to this register to the range supported by the core instance.
- IP Width In 0 (0x00100) Register
- Allows you to program the width of the first input color image which is to be scaled and written to destination buffer as the first output. Supported values are between 64 and the value provided in the Maximum Number of Columns field in the Vivado Integrated Design Environment (IDE). To avoid processing errors, restrict values written to this register to the range supported by the core instance.
- IP Width Out 0 (0x00108) Register
- Allows you to program the width of the first output color image which is to be written to the destination buffer. Supported values are between 64 and the value provided in the Maximum Number of Columns field in the Vivado Integrated Design Environment (IDE). To avoid processing errors, restrict values written to this register to the range supported by the core instance.
- IP Height In 0 (0x00110) Register
- Allows you to program the height of the first input color image which is to be scaled and written to destination buffer as the first output. Supported values are between 64 and the value provided in the Maximum Number of rows field in the Vivado Integrated Design Environment (IDE). To avoid processing errors, restrict values written to this register to the range supported by the core instance.
- IP Height Out 0 (0x00118) Register
- Allows you to program the height of the first output color image which is to be written to the destination buffer. Supported values are between 64 and the value provided in the Maximum Number of Columns field in the Vivado Integrated Design Environment (IDE). To avoid processing errors, restrict values written to this register to the range supported by the core instance.
- IP Line rate for Output 0 (0x00128) Register
- Allows you to program the Line Rate related to the first output.
- IP Pixel Rate for Output 0 (0x00130) Register
- Allows you to program the Pixel Rate related to the first output.
- IP Pixel Format In 0 (0x00138) Register
- Allows you to program the pixel format of the first input image which is to be read from the source buffer.
- IP Pixel Format Out 0 (0x00150) Register
- Allows you to program the pixel format of the first output image which is to be written to the destination buffer.
- IP Stride In 0 (0x00158) Register
- Allows you to program the stride required for the first input image.
- IP Stride Out 0 (0x00160) Register
- Allows you to program the stride required for the first output image.
- IP Address Offset of Plane 0 of Input 0 (0x00170) Register
- Allows you to program the address of the source memory buffer0 which
points to the first input image. If the IP is configured to 64-bit address
width in the Customize IP dialog box, the IP internally creates another
register in the register space by adding 0x4 to the existing buffer address
register offset. For example,
HwReg_srcImgBuf0_0_Vregister addresses are 0x00170 and 0x00174. Register addresses for all outputs are also calculated in a similar way. - IP Address Offset of Plane 1 of Input 0 (0x00190) Register
- Allows you to program the address of the source memory buffer1 which
points to the first input image.Note: For semi-planar formats such as Y_UV8, Y_UV8_20, Y_UV10, Y_UV10_420, the
srcImgBuf0_0register specifies the luma buffer and thesrcImgBuf1_0register specifies the chrome buffer. - IP Address Offset of Plane 0 of Output 0 (0x00200) Register
- Allows you to program the address of the destination memory buffer0 that points to the first output image.
- IP Address Offset of Plane 1 of Output 0 (0x00300) Register
- Allows you to program the address of the destination memory buffer1 that points to the first output image.
- IP Vertical Filter Coefficients Address for Output 0 (0x02000) Register
- Allows to program the vertical scaler filter coefficients required to generate the first output.
- IP Horizontal Filter Coefficients Address for Output 0 (0x02800) Register
- Allows you to program the horizontal scaler filter coefficients required to generate the first output.
Note: This section only explains the
registers related to the first output. The same description applies for all the
remaining seven outputs. For the address offsets of all the registers related to the
remaining seven outputs, check the top level registers of the Register Space table.