LogiCORE™ IP Facts Table | |
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Core Specifics | |
Supported Device Family 1 | Versal® ACAP, UltraScale+™ , UltraScale™ , Zynq®-7000 SoC, 7 series |
Supported User Interfaces | N/A |
Provided with Core | |
Design Files | Encrypted RTL |
Example Design | Not Provided |
Test Bench | Not Provided |
Constraints File | Not Provided |
Simulation Model | Encrypted VHDL |
Supported S/W Driver | N/A |
Tested Design Flows 2 | |
Design Entry |
Vivado® Design Suite System Generator for DSP |
Simulation | For supported simulators, see the Xilinx Design Tools: Release Notes Guide. |
Synthesis | Vivado Synthesis |
Support | |
Release Notes and Known Issues | Master Answer Record: N/A |
All Vivado IP Change Logs | Master Vivado IP Change Logs: 72775 |
Xilinx Support web page | |
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