The clk5x_wiz_v1_0 aligns with the Clock Wizard for Versal Adaptive SoCs behavior, with specific differences in PLL
primitive mapping and dynamic reconfiguration port (DRP) support.
- When PLL is selected in the Clocking Wizard (
clk_wizard_v1_0), the selected primitive is XPLL. - When PLL is selected in NOC2 Clocking Wizard (
clk5x_wiz_v1_0), the selected primitive is X5PLL.
The NOC2 Clocking Wizard (clk5x_wiz_v1_0) is
available for Versal Prime Series Gen 2, Versal Premium Series, and Versal
AI Edge Series Gen 2 families. For more information, refer
to
Versal
Adaptive SoC Clocking Resources Architecture Manual
(AM003).
Important: DRP is not supported with PLL
selection in
clkx5_wiz_0.