User Parameters - User Parameters - 1.0 English - PG321

Clocking Wizard for Versal Adaptive SoCs LogiCORE IP Product Guide (PG321)
Document_ID
PG321
Release_Date
2026-08-31
Version
1.0 English

The following table shows the relationship between the fields in the AMD Vivado™ IDE and the user parameters (which can be viewed in the tool command language (Tcl) console).

Table 1. User Parameter Description
Vivado IDE Parameter/Value User Parameter/Value Range Default Value
Component Name Component_Name - clk_wizard_v1_0
Component Name Component_Name - clkx5_wiz_v1_0 2
Primitive PRIMITIVE_TYPE MMCM, PLL, DPLL, Auto, None MMCM
Phase Alignment USE_PHASE_ALIGNMENT true, false false
Minimize Power USE_MIN_POWER true, false false
Jitter Optimization JITTER_SEL
  • Balanced: No_Jitter
  • Minimize Output Jitter: Min_O_Jitter
  • Maximize Input Jitter filtering: Max_I_Jitter
 Balanced
Secondary USE_INCLK_SWITCHOVER true, false false
Port Name PRIMARY_PORT, SECONDARY_PORT - PRIMARY_PORT Clk_in1, SECONDARY_PORT Clk_in2
Primary Input Clock (MHz) PRIM_IN_FREQ 10–1230 (range varies depending on the part/board type selected) 100.000
Secondary Input Clock (MHz) SECONDARY_IN_FREQ 72–144 100.000
Jitter Options JITTER_OPTIONS UI, PS UI
Primary Input Jitter CLKIN1_JITTER
  • PS: [10–999]
  • UI: [0.001–0.10]
 0.010
Secondary Input Jitter CLKIN2_JITTER
  • UI: [0.001–0.10]
  • PS: [10–999]
 0.010
Source PRIM_SOURCE
  • 1: Single_ended_clock_capable_pin
  • 2: Differential_clock_capable_pin
  • 3: Global_buffer
  • 4: No_buffer
 Single_ended_clock_capable_pin
Source SECONDARY_SOURCE
  • 1: Single_ended_clock_capable_pin
  • 2: Differential_clock_capable_pin
  • 3: Global_buffer
  • 4: No_buffer
 Single_ended_clock_capable_pin
Clk_out<1-7> CLKOUT_USED true, false true, false, false, false, false, false, false
Port Name CLKOUT_PORT true, false clk_out1, clkout2, clk_out3, clk_out4, clk_out5, clk_out6, clk_out7
Requested Output clock frequency CLKOUT_REQUESTED_OUT_FREQ - 100.000, 100.000, 100.000, 100.000, 100.000, 100.000, 100.000
Requested CLKOUT_REQUESTED_PHASE -360.000–360.000 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000
Requested Duty Cycle CLKOUT_REQUESTED_DUTY_CYCLE 0.001–99.99 50.0, 50.0, 50.0, 50.0, 50.0, 50.0, 50.0
Drives CLKOUT_DRIVES BUFG, BUFGCE, BUFGCE_DIV, MBUFGCE, Buffer, Buffer with CE, No_buffer BUFG, BUFG, BUFG, BUFG, BUFG, BUFG, BUFG_GT
PI Control CLKOUT_DYN_PS DESKEW_PD1, DESKEW_PD2, Fine_PS, None None, None, None, None, None, None, None
Clock Grouping CLKOUT_GROUPING Auto, CLOCK_A, CLOCK_B, CLOCK_C, None Auto, Auto, Auto, Auto, Auto, Auto, Auto
Source FEEDBACK_SOURCE
  • Automatic Control On-Chip: FDBK_AUTO
  • Automatic Control Off-Chip: FDBK_AUTO_OFFCHIP
  • User-Controlled On-Chip: FDBK_ONCHIP
  • User-Controlled Off-Chip: FDBK_OFFCHIP
 Automatic Control On-Chip
Signaling CLKFB_IN_SIGNALING
  • Single-ended: SINGLE
  • Differential: DIFF
 SINGLE
Reset USE_RESET true, false false
Powerdown USE_POWER_DOWN true, false false
Input clk stopped USE_INCLK_STOPPED true, false false
Locked USE_LOCKED true, false false
Locked_FB USE_LOCKED_FB true, false false
Locked_DESKEW1 USE_LOCKED_DESKEW1 true, false false
Locked_DESKEW2 USE_LOCKED_DESKEW2 true, false false
deskew1_delay_en DESKEW1_DELAY_EN true, false false
deskew2_delay_en DESKEW2_DELAY_EN true, false false
deskew1_delay_path DESKEW1_DELAY_PATH ClkIn_Path, ClkFb_Path ClkFb_Path
deskew1_delay DESKEW1_DELAY 0–63 0
deskew2_delay_path DESKEW2_DELAY_PATH ClkIn_Path, ClkFb_Path ClkFb_Path
deskew2_delay DESKEW2_DELAY 0–63 0
Clkfbstopped USE_CLKFB_STOPPED true, false false
Reset Type RESET_TYPE ACTIVE_HIGH, ACTIVE_LOW ACTIVE_HIGH
Phase shift Mode PHASESHIFT_MODE WAVEFORM, LATENCY LATENCY
Allow Override Mode OVERRIDE_PRIMITIVE true, false false
Bandwidth BANDWIDTH
  • MMCM: LOW, HIGH, OPTIMIZED
  • PLL: LOW, HIGH, OPTIMIZED
  • DPLL: OPTIMIZED
 OPTIMIZED
CLKFBOUT_MULT CLKFBOUT_MULT Depends on the primitive selected 30
CLKFBOUT_PHASE CLKFBOUT_PHASE -360.000–360.000 0.000
COMPENSATION COMPENSATION
  • DPLL: INTERNAL AUTO, BUF_IN, EXTERNAL
  • PLL: INTERNAL
  • MMCM: AUTO, INTERNAL, BUF_IN, EXTERNAL
 AUTO
DIVCLK_DIVIDE DIVCLK_DIVIDE Depends on the primitive selected 1
CLKFBOUT_PHASE_CTRL CLKOUTFB_PHASE_CTRL None, Fine_PS, DESKEW_PD1, DESKEW_PD2 None
Divide CLKOUT<1-7>_DIVIDE - 30
Duty Cycle CLKOUT<1-7>_DUTY_CYCLE 0–100 0.500
Phase CLKOUT<1-7>_PHASE -360.000–360.000 0.000
Locked LOCKED_PORT - Locked
Clk_in_sel CLK_IN_SEL_PORT - clk_in_sel
Reset RESET_PORT - reset
Input_clk_stopped INPUT_CLK_STOPPED_PORT - input_clk_stopped
Clkfb_stopped CLKFB_STOPPED_PORT - clkfb_stopped
Locked_FB LOCKED_FB_PORT - locked_fb
Locked_DESKEW1 LOCKED_DESKEW1_PORT - locked_deskew1
Locked_DESKEW2 LOCKED_DESKEW2_PORT - locked_deskew2
Power_Down POWER_DOWN_PORT - power_down
Dynamic Reconfig USE_DYN_RECONFIG true, false false
Spread Spectrum USE_SPREAD_SPECTRUM true, false false
Enable Clock Monitoring ENABLE_CLOCK_MONITOR true, false false
ZHOLD ZHOLD true, false false
Ss Mode SS_MODE CENTER HIGH, CENTER LOW, DOWN HIGH, DOWN LOW CENTER HIGH
Modulation Freq SS_MOD_FREQ 25–250 250
Dynamic Reconfig Interface Options INTERFACE_SELECTION Enable_AXI, Enable_APB3 Enable_AXI
Enable User Clock0 ENABLE_USER_CLOCK0 true, false false
Enable User Clock1 ENABLE_USER_CLOCK1 true, false false
Enable User Clock2 ENABLE_USER_CLOCK2 true, false false
Enable User Clock3 ENABLE_USER_CLOCK3 true, false false
User clk0 Freq USER_CLK_FREQ0 1–300 100
User clk1 Freq USER_CLK_FREQ1 1–300 100
User clk2 Freq USER_CLK_FREQ2 1–300 100
User clk3 Freq USER_CLK_FREQ3 1–300 100
Enable PLL0 Enable_PLL0 true, false false
Enable PLL1 Enable_PLL1 true, false false
Ref clk Freq REF_CLK_FREQ 1–300 100
Precision PRECISION 1–100 1
Relative Inclk RELATIVE_INCLK REL_PRIMARY, REL_SECONDARY REL_PRIMARY
Deskew1 IN DESKEW1_IN 0–9 0
Deskew1 FB DESKEW1_FB 1–7 1
Deskew2 IN DESKEW2_IN 0–9 0
Deskew2 FB DESKEW2_FB 1–7 1
Safe Clock Startup USE_SAFE_CLOCK_STARTUP true, false false
Safe Clock Startup Mode SAFECLOCK_STARTUP_MODE DESKEW_MODE, BUFGCE_MODE DESKEW_MODE
E TYPE CE_TYPE SYNC, ASYNC, HARDSYNC SYNC
BUFGCE DIV CE TYPE BUFGCE_DIV_CE_TYPE SYNC, HARDSYNC SYNC
CE and CLR SYNC Circuit External to Core CE_SYNC_EXT false, true false
Use Clock Sequencing USE_CLOCK_SEQUENCING false, true false
CLKOUT<1-7>_SEQUENCE_NUMBER CLKOUT<1-7>_SEQUENCE_NUMBER 1–7 1
  1. Parameter values are listed in the table where the Vivado IDE parameter value differs from the user parameter value. Such values are shown in this table as indented below the associated parameter.
  2. The clkx5_wiz_v1_0 differs from the standard Clocking Wizard in PLL primitive mapping and DRP support. The clkx5_wiz_v1_0 is available for the Versal Prime Series Gen 2, Versal Premium Series, Versal AI Edge Series Gen 2 families and the XCVM2152 devices. For details, refer to clk5x_wiz_v1_0 Differences.