Simulation Waveforms for the Safe Clock Startup Feature Without Sequencing - Simulation Waveforms for the Safe Clock Startup Feature Without Sequencing - 1.0 English - PG321

The following figure shows simulation, when Safe Clock Startup is true.

The sequencing is disabled in the preceding configuration.

• After LOCKED is high, clk_out1 enables after 8 cycles to first clock out the frequency of primitive. Similarly, after LOCKED is high, clk_out2 enables after 8 cycles to second clock out the frequency of primitive.
• Similarly, after LOCKED is high, clk_out3 enables after 8 cycles to third clock out frequency of primitive.
• Similarly, after LOCKED is high, clk_out4 enables after 8 cycles to fourth clock out frequency of primitive.