Simulation Waveforms for the Safe Clock Startup Feature With Sequencing - Simulation Waveforms for the Safe Clock Startup Feature With Sequencing - 1.0 English

Simulation Waveforms for the Safe Clock Startup Feature With Sequencing - Simulation Waveforms for the Safe Clock Startup Feature With Sequencing - 1.0 English - PG321

Clocking Wizard for Versal Adaptive SoCs LogiCORE IP Product Guide (PG321)

Document_ID

PG321

Release_Date

2026-08-31

Version

1.0 English

The following figure shows simulation when Safe Clock Startup is true and Use Clock Sequencing is true, with the required sequence number in the table (consider sequence 1,2,3,4).

Figure 1. Simulation, when Safe Clock Startup is true and Use Clock Sequencing

After LOCKED is high, clk_out1 enables after 8 cycles to the first clock out the frequency of primitive.And after CLKOUT1 is high, clk_out2 enables after 8 cycles to the second clock out the frequency of primitive.
After CLKOUT2 is high, clk_out3 enables after 8 cycles to the third clock out frequency of primitive.
After CLKOUT3 is high, clk_out4 enables after 8 cycles to the fourth clock out frequency of primitive.

This is useful if the clocks need to come in sequence.