This mode selection determines how the hardware structure need to be for the selected outputs.
The options for this mode are DESKEW_MODE and BUFGCE_MODE.
DESKEW_MODE helps operate the clocking circuit for high frequencies compared to BUFGCE_MODE selection. Hence, DESKEW_MODE is the default value for this parameter.
DESKEW_MODE cannot be selected if you have more than two output clocks in MMCM/XPLL (as there are a maximum of two deskew networks present for MMCM/PLL), and this mode is not supported for DPLL because of deskew connection rules restriction.
Versal adaptive SoCs offer a new CE_TYPE property, which lets you specify if the CE input to the BUFGCE is timed (CE_TYPE=SYNC) or uses an internal 3-stage synchronizer (CE_TYPE=HARDSYNC). In the case of HARDSYNC, the CE path is not timed (CE timing arc disabled), and the BUFGCE is enabled within three or four clock cycles. However, there is no guarantee that all the BUFGCE in a clock region that employ the CE_TYPE=HARDSYNC 3-stage synchronizer are enabled within the same number of clock cycles.
- DESKEW_MODE are not possible in DPLL, as
clkin_deskewconnection in DPLL must be from clock input, so in DPLL, Only BUFGCE mode is allowed. - When you select DESKEW_MODE, set CE_TYPE to
SYNC. - When you select BUFGCE_MODE, by default, CE_TYPE is set to
HARDSYNC, but you can change the value to other CE Type. - In any mode, timing is not guaranteed beyond a certain frequency (Frequency vary for each speed grade).
- In DESKEW_MODE, you need to manually modify or adjust the deskew delay to improve the timing to resolve the timing issue.
- For more details, refer to Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387).