Migrating to the Vivado Design Suite - Migrating to the Vivado Design Suite - 1.0 English - PG321

Clocking Wizard for Versal Adaptive SoCs LogiCORE IP Product Guide (PG321)

Document_ID
PG321
Release_Date
2026-08-31
Version
1.0 English

For information about migrating to the AMD Vivado™ Design Suite, refer to ISE to Vivado Design Suite Migration Guide (UG911).

Note: You cannot migrate to an AMD Versal™ Clocking Wizard from a Non-AMD Versal™ Clocking Wizard as they both are two separate IPs. A new IP must be built from scratch with similar properties.

For example, you have a requirement of two output clocks with clk_out1 as 120 MHz and clk_out2 as 150 MHz and a separate phase/duty cycle requirement for two clocks. In Non-Versal, you pass a value for each clock attribute, whereas, in Versal, the parameters must be provided as a string for all the output clocks when using batch mode. For example, if you want to feed the requested clock frequencies for the clocks, the parameter CLKOUT_REQUESTED_OUT_FREQ must be assigned a value of 120, 150, 100, 100, 100, 100, and 100 (100 is the default value). It is the combination of all output frequencies from 1 to 7. If the string does not contain seven values, it fills the initial frequencies, and for the rest, it takes the default value. Similarly, for all other parameters of CLKOUT_DRIVES, CLKOUT_DYN_PS, CLKOUT_MATCHED_ROUTING, CLKOUT_REQUESTED_DUTY_CYCLE, CLKOUT_REQUESTED_PHASE, CLKOUT_USED, and CLKOUT_PORT, you must pass the respective values as a list of values in batch mode instead of a single value for each clock.

  • PRIMITIVE, which can be "MMCM, PLL, Auto" in Non-Versal, can be mapped to the PRIMITIVE_TYPE parameter.
  • OVERRIDE_MMCM, which can set to “True/False” needs to map to the OVERRIDE_PRIMITIVE parameter.