|
Core Specifics |
| Supported Device Family
1
|
Versal®
ACAP |
| Supported User Interfaces |
AXI4-Lite
|
| Resources |
Resource Use
|
| Special Features |
MMCM, XPLL, DPLL, Auto, Primitive Override, Spread Spectrum,
Dynamic Reconfiguration, Clock Monitor, Auto Buffer, Clock Grouping, Safe Clock
Startup, Analog/Digital deskew and MBUFGCE |
| Provided with
Core
|
| Design Files |
Verilog
2
|
| Example Design |
Verilog |
| Test Bench |
Verilog
2
|
| Constraints File |
Xilinx®
Design Constraints |
| Simulation Model |
For supported simulators, see the Xilinx Design Tools: Release Notes
Guide
|
| Instantiation Template |
Verilog and VHDL Wrapper |
| Supported S/W Driver
2
|
Not Applicable |
| Tested Design Flows
3
|
| Design Entry |
Vivado® Design Suite
|
| Simulation |
Mentor Graphics QuestaSim, Vivado Simulator. For supported simulators, see the Xilinx Design Tools: Release Notes
Guide. |
| Synthesis |
Vivado Synthesis |
| Support |
|
Xilinx
Support web page
|
| Release Notes and Known Issues |
Master Answer Record: AR 76369
|
| All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775
|
- For a complete list of supported devices, see
the Vivado IP catalog.
- Standalone driver details can be found in the
Vitis directory (<install_directory>/Vitis/<release>/data/embeddedsw/doc/xilinx_drivers.htm).
Linux OS and driver support information is available Xilinx Wiki page.
- For the supported versions of the tools, see
the Xilinx Design Tools: Release Notes
Guide.
|