Example for Dynamic Reconfiguration Through AXI4-Lite - Example for Dynamic Reconfiguration Through AXI4-Lite - 1.0 English - PG321

Clocking Wizard for Versal Adaptive SoCs LogiCORE IP Product Guide (PG321)
Document_ID
PG321
Release_Date
2026-08-31
Version
1.0 English

The input and output clock frequencies are 100 MHz in the Clocking Wizard by default.

  1. The output clock frequency needs to be reconfigured to 50 MHz with a phase shift of 90 degrees.
  2. The following file gets generated in the sources area.

  3. The file specifies all the AXI Registers with the address and the data which needs to be written into it. Configure all the AXI Registers with respect to the table.
  4. Configure the address: C_BASEADDR + 0x014 with 0x00000003 to set the LOAD and SEN bits.
  5. Wait for the locked signal. The new frequency can be checked at clkout1 output port.
Note:
  1. DRP interface is not supported for AMD Versal™ devices, APB3 interface is used internally. For details on DRP/APB3 ports, refer to Versal Adaptive SoC Clocking Resources Architecture Manual (AM003). When using DRP, the Reset of the MMCM/PLL is driven by a state machine within the wizard. Because of this, the reset port is not exposed in the wizard. The clocking wizard can be reset by driving the s_axi_aresetn AXI4 signal.
  2. While reconfiguring, even reconfiguring for one clock output, all other active clock outputs reset.
  3. When using Dynamic Reconfiguration, the Reset of the MMCM/PLL is driven by a state machine within the wizard. Because of this, the reset port is not exposed in the wizard. The clocking wizard can be reset by driving the s_axi_aresetn AXI-4 signal.