Dynamic Reconfiguration Through AXI4-Lite - Dynamic Reconfiguration Through AXI4-Lite - 1.0 English - PG321

The Clocking Wizard core provides an AXI4-Lite interface for dynamic reconfiguration of the MMCM, XPLL, and DPLL clocking primitives. This interface is enabled when the Dynamic Reconfiguration option is enabled. When the AXI4-Lite interface is selected, the core delivers mixed-language RTL.

Register Space provides details of the signals of AXI4-Lite and the tables provide details of the clock configuration registers.

The Clocking Wizard core uses a configuration state machine listed in and extends from two fixed state configuration to program any valid range of multiply, divide, phase, and duty cycle. In this state machine, State 1 corresponds to default state configured through Clocking Wizard interface. State 2 corresponds to user-configuration loaded into the clock configuration register detailed in the tables in Register Space. State 2 values are also initialized with the State 1 values so that a valid configuration is stored by default. All the dynamic reconfiguration registers are to be updated whenever you want to reprogram the clock.

Perform the following steps for dynamic reconfiguration:

1. Generate the Clocking Wizard IP enabling dynamic reconfiguration.
2. Open another Clocking Wizard with the same input clock and the features as intended.
3. Now, change the output clock features in the output clock tab of the AMD Vivado™ IDE as required for dynamic reconfiguration.
4. Generate the IP.
5. A file with name <component_name>_drp_address_map generates in the IP sources area. This file has the address and the data which needs to be written into AXI interface for reconfiguring.
6. After writing all the registers in the file, now write address 0x014 with 0x03 as mentioned in the register map to initiate the reconfiguration.

The following section describes an example of this feature.