DPLL Soft Calibration Logic - DPLL Soft Calibration Logic - 1.0 English - PG321

Clocking Wizard for Versal Adaptive SoCs LogiCORE IP Product Guide (PG321)

Document_ID
PG321
Release_Date
2026-08-31
Version
1.0 English

The soft calibration logic minimizes the DCO fluctuations in the DPLL. During an initial calibration period, CLKOUT3 is reprogrammed to cover frequencies spanning the entire DCO frequency range. After calibration completes, the original CLKOUT3 settings are restored. As the DPLL switches between settings, the DCO frequencies overlap, and the JUMP values allow the DPLL to switch between the settings while minimizing DCO fluctuations.

If calibration logic is not used, unexpected behavior can occur, such as the following:

  • The DPLL does not guarantee jitter performance without the calibration logic.
  • The DPLL can under-report jitter, which can affect STA.
  • The DPLL can experience locking issues.