This chapter introduces the Clocking Wizard core and provides related information, recommended design experience, additional resources, technical support, and ways of submitting feedback to AMD. The Clocking Wizard core generates source register transfer level (RTL) code to implement a clocking network matched to your requirements. Both Verilog and VHDL design instantiation templates are supported.
The Clocking Wizard core is an AMD IP core that can be generated using the AMD Vivado™ design tools, included with the latest Vivado Design Suite release in the Download page.