Configuring Output Clocks - Configuring Output Clocks - 1.0 English - PG321

To enable an output clock, click on the box located next to it. Output clocks must be enabled sequentially. You can now rename the output clocks in the output clock table itself.

You can specify values for the output clock frequency, phase shift, and duty cycle assuming that the primary input clock is the active input clock. You can select drives, clock grouping and PI control for each output clock.

The Clocking Wizard attempts to derive a clocking network that meets your criterion exactly. In the event that a solution cannot be found, best attempt values are provided and are shown in the actual value column. Actual frequencies are calculated to limit the values to five decimal places.

Achieving the specified output frequency takes precedence over implementing the specified phase, and phase takes higher precedence over duty cycle in the clock network derivation process. The precedence of deriving the circuits for the clk_out signals is clk_out1 > clk_out2 > clk_out3 and so on. Therefore, finding a solution for clk_out1 frequency has a higher priority. Values are recalculated every time an input changes. Because of this, it is best to enter the requirements from top to bottom and left to right. This helps to pinpoint requested values that cannot be supported exactly.

If phase alignment is selected, the phase shift is with respect to the active input clock.