The Clock Stop goes high when the clock is flat-lined for more than 10
clock cycles. The clock is stale for 10 or more clock cycles, it initiates the
calculation to detect the stop and signals the clk_stop
high. The clk_stop signal does not become high
immediately and can take up to 256 clock cycles from the time the clock is flat. This
calculation requires a set of reference clock cycle periods, time at which the clk_stop go high depends on the ratio of user_clk and ref_clk.