PHY Implementation - 1.0 English - PG320

The Versal architecture IP defines using a pre-engineered test bench and PHY for interfacing user designs. This IP is structured so that only the physical layer (PHY) interconnect in the AMD device should be updated when pinouts change. Because the PHY implementation depends on the I/O assignments, it must occur after the I/Os are placed and validated. To enable I/O Planning after synthesis, the implementation of the PHY now happens as part of implementation during the opt_design command.