FIFO Modes - 1.0 English - PG320

The FIFO_MODES GUI option allows you to select different modes supported by XPHY. This feature is currently in beta mode. Following are the different FIFO modes:

Sync Mode

In this mode, FIFO_RD_CLK and FIFO_WR_CLK are equal. FIFO_RD_CLK must be driven by a BUFG connected to FIFO_WR_CLK. FIFO_RD_EN is controlled by a new parameter called FIFO read enable control that connects the FIFO_RD_EN signal to the inverse of FIFO_EMPTY.

Async Mode

It is a default FIFO mode with FIFO_RD_CLK and FIFO_WR_CLK.

Bypass Mode

In this mode, FIFO_WR_CLK is the output from XPHY. FIFO_RD_CLK, FIFO_RD_EN, and FIFO_EMPTY are masked at bank wrapper level. FIFO_RD_EN is connected to logic Low level and FIFO_EMPTY is connected to logic High level.

Important: For SYNC and BYPASS, FIFO_WR_CLK is driven by the strobe input for source synchronous designs. Use FIFO_WR_CLK with clock buffers for simple interfaces where performance is not critical. To improve performance, an external FIFO_WR_CLK deskew circuit with an additional PLL might be required (not shown in example designs). For more information, see the details of the FIFO_WR_CLK deskew circuit in the Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010).

Figure 1. FIFO Modes

Following are the user parameters of the FIFO mode: