- FIFOMODE_#_SYNC shows how the first two pins within a BUS0 can
change the FIFO_MODE_# to SYNC in the XPHY
settings.
set_property CONFIG.BUS0_XPHY_ATTR {FIFOMODE_0_SYNC, FIFOMODE_1_SYNC} [get_ips advanced_io_wizard_0] - If you pass both the broadcast (nibble level) and bit/pin level attribute
values, the broadcast gets priority over bit/pin level values. Each bus must contain
all settings within a single property. In this example, BUS0_XPHY_ATTR sets BYPASS
for the nibble as well as SYNC for two of the
bits/pins.
set_property CONFIG.BUS0_XPHY_ATTR {FIFOMODE_0_SYNC, FIFOMODE_1_SYNC , FIFOMODE_BYPASS} [get_ips advanced_io_wizard_0]To confirm the BUS0_XPHY_ATTR has been set correctly, use get_property to read back the current setting for BUS0_XPHY_ATTR.get_property CONFIG.BUS0_XPHY_ATTR [get_ips advanced_io_wizard_0] - If a strobe is present, S0 is passed at bit/pin level as FIFOMODE_S0_SYNC
and if the write clock is present the in case of BIDIR mode, W0 is passed as
FIFOMODE_W0_SYNC from the Tcl console. After these values are passed, data pins
always start from 0th position.
set_property CONFIG.BUS0_XPHY_ATTR {FIFOMODE_S0_SYNC , FIFOMODE_0_SYNC , FIFOMODE_1_SYNC} [get_ips advanced_io_wizard_0]
If you have one strobe and two single-ended data pins enabled:
- For differential pairs, both P and N need to be changed at the bit/pin level.
- Rule engine errors have a higher priority over the user input.
- The advanced bit mode changes are applicable to both IP and example design.