For asynchronous receive applications that are not covered by the CDR with PPM difference or CDR with zero PPM, you might prefer to create your own CDR circuitry. The custom clock data recovery (CDR) option enables you to attach an independent CDR block in your design. The custom CDR logic exposes IP ports directly from XPHY as shown in the following figure. Custom CDR is valid only for RX and asynchronous applications.
For example, if the interface speed is 1250 Mb/s, the PLL clock frequency
should be 1250 MHz. Similar to CDR with PPM, XPHY is configured with SERIAL_MODE = TRUE,
RX_DATA_WIDTH = 8; therefore, the expected FIFO_RD_CLK frequency is F_FIFO_RD_CLK =
REFCLK_FREQUENCY * 2 / RX_DATA_WIDTH = 1250 * 2 / 8 = 312.5 MHz. For custom CDR,
bank0_pll_clkout2 is set up to drive
fifo_rd_clk.