| FIFO_RD_CLK |
Input |
Async |
Clock provided to PHY FIFO_CLK to drive XPHY and CDR
logic. |
| CTRL_CLK |
Input |
Async |
Clock provided to PHY CTRL_CLK to drive XPHY and CDR
logic. |
| intf_rdy |
Input |
Async |
Output of XPHY and input to custom CDR. |
| FIFO_EMPTY |
Input |
Async |
To start reading the data once FIFO_EMPTY is de-
asserted. |
| PHY_RDEN |
Output |
Async |
To allow FIFO to start filling in PHY, input to the XPHY and output of
custom CDR. |
| FIFO_RDEN |
Output |
Async |
Assert when you want to start reading data from PHY and output of
custom CDR. |
| Data_to_fabric_*(Bitslice data) |
Input |
Async |
Output data of PHY per bitslice. Each bitslice provides 8-bit
data. |
| CNTVALUEOUT |
Output |
Async |
Input to PHY per bitslice to update delay line value and output
of custom CDR. |
| CNTVALUEIN |
Input |
Async |
Updated Value of CNTVALUE from PHY and input to custom
CDR. |
| CE |
Output |
Async |
Control signals inputs for updating delay line per bitslice and
output of custom CDR. |
| INC |
Output |
Async |
Control signals inputs for updating delay line per bitslice and
output of custom CDR. |
| LD |
Output |
Async |
Control signals inputs for updating delay line per bitslice and
output of custom CDR. |
| RXTX_SEL |
Output |
Async |
Control signals inputs for updating delay line per bitslice and
output of custom CDR. |