The XPLLs associated with each bank are the primary source for clocking the SelectIO™ resources in the bank. You can select the source of the input reference clock to XPLL. The source can be a clock from the global clock pin (GC) or from the global clock network through BUFG. You can also select the input clock frequency from AMD Vivado™ IDE, which lists all the supported clocks for a given device. For more information, see Versal Adaptive SoC Clocking Resources Architecture Manual (AM003).