Management Requests and AXI4-Lite - Management Requests and AXI4-Lite - 5.0 English - PG319

Semi-Ternary CAM Search v5.0 LogiCORE IP Product Guide (PG319)

Document ID
PG319
Release Date
2025-11-26
Version
5.0 English

All Read and Write Management Requests are 64 bits wide. The only exception occurs for insert and update operations of the entry. The insert and update operations write whole entries. Size of a management request is always a multiple of 64 bits. For example, if the entry width is 512 bits then the insert or update operation uses a 512-bit wide management request.

The AXI4-Lite bus uses 13 bits of address and 32 bits of data, so for every Management Request multiple AXI4-Lite writes are issued from the API software. The AXI4-Lite writes are assembled by the secondary AXI4 to a single Management Request. The AXI4-Lite interface is a standard type. Refer to AXI4-Lite IPIF LogiCORE IP Product Guide (PG155).

Note: AXI4-Lite imposes the following requirements when switching between read and write:
  • All outstanding write responses must have been received before issuing a read.
  • All outstanding read responses must have been received before issuing a write.

The following table shows an example calculation for 100 Gb Ethernet rate. Keep in mind the calculated update rate only refers to the hardware resources, the final update rate is most likely limited by the table management software.

Table 1. 100 GbE Update Rate Example Calculation (Hardware Limit)
Management Request Size [bits] AXI4-Lite Write Operations [min / max] Management Update rate [M updates/s]
64 1 / 3 4.8
128 2 / 5 4.8
256 4 / 9 4.8
512 8 / 17 4.8
1024 16 / 33 4.8
  1. Parameters used in this fixed rate STCAM example: LOOKUP_RATE = 148.8, RAM_FREQ = 600, TDM_FACTOR = 4
  2. The AXI4-Lite maximum number of write operations applies for random data patterns. Minimum number of operations can be achieved when the write data is constant (for example, initializing to zero).