Hardware issues can range from link bring-up to problems seen after hours of testing. This section provides debug steps for common issues. The AMD Vivado™ debug feature is a valuable resource to use in hardware debug. The signal names mentioned in the following individual sections can be probed using the debug feature for debugging the specific problems.
Software Driver Bringup
The software driver is started by calling cam_create
(bcam_create, stcam_create, or
tcam_create, to be precise). The following debug flag setting is
recommended during bringup:
-
CAM_DEBUG_ARGS -
CAM_DEBUG_CONFIG -
CAM_DEBUG_VERBOSE_VERIFY
The driver reads several configuration parameters from hardware and verifies that they
match with the input values provided to cam_create.
The write operation is tested using a scratch register. A value is written and read back for verification.
Possible sources of problems are issues in AXI4-Lite connectivity and base address mismatches between software and hardware.
A successful return status from cam_create is necessary before proceeding
with insert/update/delete operations.
Inserting Entries
The bcam_insert/stcam_insert/tcam_insert
driver functions write entries to hardware. The following debug flags are recommended when
debugging insert operations:
-
CAM_DEBUG_ARGS -
CAM_DEBUG_VERIFY_WR -
CAM_DEBUG_VERBOSE_VERIFY
The debug flag CAM_DEBUG_VERIFY_WR reads back all written data. This
verifies that entries are stored correctly in the CAM.
Lookup Operations
The lookup operations are performed using the AXI4-Stream datapath and are
not directly accessible by software. The most recent lookup operation can be inspected using
the statistics API (bcam_get_stats, stcam_get_stats,
tcam_get_stats).
The STATISTICS parameter must be enabled in the IP generator GUI when the instance is generated.
The following debug flags are recommended for lookup debug:
-
CAM_DEBUG_ARGS -
CAM_DEBUG_STATS
CAM_DEBUG_HW_LOOKUP can only be
used during Verilog simulation. It prints key/response and match status for lookup
operations.| Port Name | Description | Clock Domain [SINGLE_CLOCK / DUAL_CLOCK] |
|---|---|---|
| debug_status[0] | Address decoding failed for write operation (unknown address – possibly caused by mismatch between software and hardware configuration parameters) | key_clk / ram_clk |
| debug_status[1] | Address decoding failed for read operation (unknown address – possibly caused by mismatch between software and hardware configuration parameters) | key_clk / ram_clk |
| debug_status[2] | AXI read data FIFO overflow (read data is not accepted fast enough) | key_clk / ram_clk |
| debug_status[3] | AXI write response FIFO overflow (write response channel not responding fast enough) | s_axi_clk |
| debug_status[4] | AXI read/write request FIFO overflow. Read/write operations are
not executed fast enough. Possible problems:
|
s_axi_clk |
| debug_status[5] | Lookup Request FIFO overflow (ram_clk frequency is too low compared to key_clk frequency, or actual lookup rate is higher than the configured lookup rate) | key_clk |
| debug_status[6] | Lookup Response FIFO overflow (ram_clk frequency is too high compared to key_clk frequency) | key_clk / ram_clk |
| debug_status[7] | Unused | |
| debug_status[8] | Write Busy: An insert/update/delete operation is ongoing. | key_clk |
| debug_status[9] | Lookup Busy: A lookup operation is ongoing. | key_clk |
| debug_status[31:10] | Unused |