- Associative array containing arbitrary (key, mask, priority, response) entries.
- Ternary match key lookup returns hit/miss result and associated response value on hit.
- High throughput: one lookup per clock cycle at 600 MHz.Note: Achievable clock frequencies will depend on the device being used, the resources used by the CAM configuration, and the congestion in the device.
- Flexible: supports a wide range of key widths, response widths and lookup rates with optimized resource utilization.
- Up to eight 32-bit wide range comparison fields in each rule minimizes the need for costly rule expansion.
- Optimized usage options: Fixed version offers more accurate rate and latency values. Variable version is intended for low cost applications and corner cases that allows some degradation in rate and latency values.
- Supports all key widths up to 992 bits and all response widths up to 1024 bits.
- Supports both UltraRAM (URAM) and block RAM implementations.
- Scalable: supports one or multiple STCAM instances, each instance can use all of the block RAM/URAM within an SLR allowing very large STCAMs.
- High storage efficiency: up to 95% of the RAM bits are transformed to CAM bits.
- Supports error correction coding (ECC). Single-bit errors are corrected dynamically during lookups, and permanently with scrubbing.
- Supports AMD Vivado™ IP integrator.
- Supports entry insert, delete, update using standard TCAM like software APIs.
- Can be inferred from within P4 code using the AMD Vitis™ Networking P4 (VitisNetP4) tool.