Performance - Performance - 5.1 English - PG318

Ternary CAM Search v5.1 LogiCORE IP Product Guide (PG318)
Document ID
PG318
Release Date
2026-07-08
Version
5.1 English

Maximum Frequencies

The Ternary CAM Search IP is designed to run at up to 500 MHz (low voltage)/600 MHz (mid voltage) for -2 speed grade devices.

Latency

The TCAM lookup latency depends on the size of the TCAM, the TDM factor and the memory type. The lookup latency is constant per configuration and some examples are shown in the following table.

Table 1. Lookup Latency
Entries TDM Factor = 1 TDM Factor = 4 TDM Factor = 16 TDM Factor = 32
256 21 16 11 10
1K 21 16 11 11
4K 21 17 11 11
16K 25 17 11 11
  1. Latency values are measured in Lookup Interface Frequency cycles.
  2. KEY_WIDTH = 104, RESPONSE_WIDTH = 16, LOOKUP_RATE = LOOKUP_INTERFACE_FREQ = 15M

Throughput

The lookup throughput corresponds to the LOOKUP_RATE parameter. The highest possible lookup throughput is accomplished when LOOKUP_RATE equals the RAM _FREQ parameter. One Lookup Request can then be issued per RAM clock cycle. The Management Request has strictly lower priority than the Lookup Request, consequently the Management Request throughput becomes:

Management Request Rate = RAM_FREQ - LOOKUP_RATE*TDM_FACTOR.

The ECC scrubbing process has the lowest priority. A memory read followed by a potential corrective write is only executed if both the Lookup Request and Management Request FIFOs are empty. Neither the lookup throughput nor the Management Request throughputs are affected. ECC scrubbing of a new address is only initiated if both FIFOs are empty and a potential pending corrective write has been executed.

Management Requests and AXI4-Lite

All Read and Write Management Requests are 64 bits wide. The only exception occurs for insert and update operations of the entry. The insert and update operations write whole entries. Size of a management request is always a multiple of 64 bits. For example, if the entry width is 512 bits then the insert or update operation uses a 512-bit wide management request.

AXI4-Lite supports configurable widths: a minimal 13-bit address/32-bit data mode and extended modes with 64-bit data and wider addresses to avoid address-indirection overhead. In minimal mode, each 64-bit management request from the driver is split into multiple AXI4-Lite operations. In wider modes (64-bit data with extended addressing), the same requests need fewer transactions, improving management performance.

The AXI4-Lite writes are assembled by the AXI4-Lite interface logic into single management requests regardless of the interface width configuration. The AXI4-Lite interface is a standard type. Refer to AXI4-Lite IPIF LogiCORE IP Product Guide (PG155).

Note: AXI4-Lite imposes the following requirements when switching between read and write:
  • All outstanding write responses must be received before issuing a read.
  • All outstanding read responses must be received before issuing a write.

The following table shows an example calculation for 100 Gb Ethernet rate. Keep in mind the calculated update rate only refers to the hardware resources, the final update rate is most likely limited by the table management software.

Table 2. 100 GbE Update Rate Example Calculation (hardware limit)
Management Request Size [bits] AXI4-Lite Write Operations [min / max] Management Update rate [M updates/s]
64 1 / 3 4.8
128 2 / 5 2.4
256 4 / 9 1.2
512 8 / 17 0.6
1024 16 / 33 0.3
Note: Parameters used in this example: LOOKUP_RATE = 148.8, RAM_FREQ = 600, TDM_FACTOR = 4, AXI_ADDR_WIDTH = 13, and AXI_DATA_WIDTH = 32.
Note: The AXI4-Lite maximum number of write operations applies for random data patterns. Minimum number of operations can be achieved when the write data is constant (for example, initializing to zero).