Transmit Clocks - 2.3 English

Versal Devices Integrated 100G Multirate Ethernet MAC Subsystem Product Guide (PG314)

Document ID
PG314
Release Date
2024-05-30
Version
2.3 English
The following describes the transmit clocks in the MRMAC.
tx_core_clk[3:0]
This internal high-speed clock drives the bulk of the MRMAC transmit datapath. This per-port clock must be generated by the GT transceiver.
tx_alt_serdes_clk[3:0]
This is an internally-used clock derived from the primary SerDes clocks. These clocks run at exactly half the tx_core_clk[3:0] frequencies. This clock is typically generated by the IP Wizard.
tx_flexif_clk[3:0]
This is used by the flex interface. When the Flex I/F is active, tx_flexif_clk[N] must operate at a frequency ≥ 1/2 of the corresponding tx_core_clk[N] frequency.
tx_axi_clk[2][0]
AXI4-Stream interface clocks. In addition to clocking the AXI4-Stream interface in independent clocking mode, the tx_axi_clk[2][0] clocks are also used only to clock certain statistics and flow control signals. The tx_axi_clk[2][0] clocks must operate at a frequency high enough to maintain the desired data rate across the AXI4-Stream bus, which is tx_axi_clk[N] must be greater than or equal to 1/2 of the corresponding tx_core_clk[N] frequency.
tx_ts_clk[3:0]
This clock drives the 1588 timestamping signaling. The MRMAC timestamp timers attempt to synchronize with the external time-of-day source which is running on this clock.
Table 1. Transmit Clock Data Rate
Selected Data Rate AXI Clock Minimum Frequency (MHz) AXI4-Stream Segment Mode Port AXI4-Stream MODE_REG Field ctl_axis_cfg_<N>
100GE 390.625 Non-Segmented 3’b101
322.265 Segmented 3’b111
40/50GE 322.265 Non-Segmented All
25GE

25GE

390.625 Non-Segmented 3’b001
322.265 Non-Segmented 3’b101
10GE 322.265 Non-Segmented All