Timer Block Diagram - 2.3 English

Versal Devices Integrated 100G Multirate Ethernet MAC Subsystem Product Guide (PG314)

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2.3 English

The architecture of the PTP timer is shown in the following figure.

Figure 1. System Timer and Adjustment Inputs Diagram (MRMAC Internal)
Note: The ctl_ptp_st_sync represents ctl_rx_ptp_st_sync and ctl_tx_ptp_st_sync.
The heart of the timer is an accumulator with a programmable periodic increment. You can specify the initial timer value and the increment value. These values can be further adjusted, if necessary, using various optional correction methods (including phase and frequency adjustments) to achieve improved accuracy between the system timer and the master TOD timer.

The main elements of the system timer include:

MRMAC timer, source of generated timestamps.
Timer Increment
The amount by which system_timer is incremented each clock period. The amount of increment can be set or adjusted as needed to synchronize the system_timer with the external master clock. The established increment can also be temporarily bypassed to provide a specific timer adjustment.
A one-shot overwrite of the system_timer value, triggered by a transition of ctl_ptp_st_sync while ctl_tx/rx_ptp_st_overwrite input signal is set.
The generated timestamp to the system, micro-adjusted to account for any desired latency by the value ctl_ptp_latency_adj.