Simulation Speed Up - 3.1 English - PG314

Versal Devices Integrated 100G Multirate Ethernet MAC Subsystem Product Guide (PG314)
Document ID
PG314
Release Date
2025-09-02
Version
3.1 English

Simulation can take a long time to complete due to the time required to complete alignment. A `define SIM_SPEED_UP is available to improve simulation time by reducing the PCS lane alignment marker (AM) spacing to speed up the time the IP takes to achieve alignment. Setting `define SIM_SPEED_UP changes the following parameters:

  • CTL_TX_VL_LENGTH_MINUS1_100GE_0 and CTL_RX_VL_LENGTH_MINUS1_100GE_0 from 16'h3FFF to 16'h01FF
  • CTL_TX_VL_LENGTH_MINUS1_25GE_0 and CTL_RX_VL_LENGTH_MINUS1_25GE_0 from 16'h4FFF to 16'h04FF
  • CTL_TX_VL_LENGTH_MINUS1_25GE_1 and CTL_RX_VL_LENGTH_MINUS1_25GE_1 from 16'h4FFF to 16'h04FF
  • CTL_TX_VL_LENGTH_MINUS1_25GE_2 and CTL_RX_VL_LENGTH_MINUS1_25GE_2 from 16'h4FFF to 16'h04FF
  • CTL_TX_VL_LENGTH_MINUS1_25GE_3 and CTL_RX_VL_LENGTH_MINUS1_25GE_3 from 16'h4FFF to 16'h04FF

The SIM_SPEED_UP option can be used for simulation when in serial loopback or if the AM spacing can be reduced at both endpoints. This option is compatible with the example design simulation, which uses serial loopback.

Note: Altering the value of CTL_TX_VL_LENGTH_MINUS1_100GE_0 and CTL_RX_VL_LENGTH_MINUS1_100GE_0 from the default value of 0x3FFF or CTL_TX_VL_LENGTH_MINUS1_25GE_* and CTL_RX_VL_LENGTH_MINUS1_25GE_* from the default values of 16'h4FFF violates the IEEE 802.3 spec.

Decreasing the AM spacing results in less than MRMAC bandwidth being available on the link.

This change can be made only in simulation. For a design to work in hardware, the default values must be used.

Full rate simulation without the SIM_SPEED_UP option should still be run.

SIM_SPEED_UP is available only when running RTL simulations. The option is not available for post-synthesis or post-implementation simulations.