PTP SYSTIMER BUS Interface - 3.1 English - PG314

Versal Devices Integrated 100G Multirate Ethernet MAC Subsystem Product Guide (PG314)
Document ID
PG314
Release Date
2025-09-02
Version
3.1 English

The PTP SYSTIMER BUS Interface is an encrypted RTL module used to demonstrate the system timer bus control. It demonstrates the generation of the st_sync pulse every 64 ns, converts the ToD timer value to CF format, and provides it to system timer interface of the core. The following table lists the port details.

Table 1. PTP SYSTIMER BUS Interface
Signal Direction Description
ts_clk I Time-stamp clock. Default clock period of 4.0 ns
rst I Reset sync with ts_clk
tx_tod_sec[47:0] I Port TX Timer seconds field
tx_tod_ns[31:0] I Port TX Timer nanoseconds field
rx_tod_sec[47:0] I Port RX Timer seconds field
rx_tod_ns[31:0] I Port RX Timer nanoseconds field
tx_tod_corr[63:0] I Port TX Timer CF format
rx_tod_corr[63:0] I Port RX Timer CF format
mrmac_tx_ptp_systimer[54:0] O MRMAC TX system timer. This needs to be connected to MRMAC IP port ctl_tx_ptp_systemtimer[54:0]
mrmac_tx_ptp_st_sync O MRMAC TX st_sync pulse. This needs to be connected to MRMAC IP port ctl_tx_ptp_st_sync
mrmac_tx_ptp_st_overwrite O MRMAC TX st_overwrite. This needs to be connected to MRMAC IP port ctl_tx_ptp_st_overwrite
mrmac_rx_ptp_systimer[54:0] O MRMAC RX system timer. This needs to be connected to MRMAC IP port ctl_rx_ptp_systemtimer[54:0]
mrmac_rx_ptp_st_sync O MRMAC RX st_sync pulse. This needs to be connected to MRMAC IP port ctl_rx_ptp_st_sync
mrmac_rx_ptp_st_overwrite O MRMAC RX st_overwrite. This needs to be connected to MRMAC IP port ctl_rx_ptp_st_overwrite
mrmac_tx_ptp_st_adjust[31:0] O MRMAC TX st_adjust value. This needs to be connected to MRMAC IP port ctl_tx_ptp_st_adjust[31:0]
mrmac_tx_ptp_st_adjust_type[1:0] O MRMAC TX st_adjust type. This needs to be connected to MRMAC IP port ctl_tx_ptp_st_adjust_type[1:0]
mrmac_tx_ptp_st_adjust_vld O MRMAC TX st_adjust valid. This needs to be connected to MRMAC IP port ctl_tx_ptp_st_adjust_vld
mrmac_rx_ptp_st_adjust[31:0] O MRMAC RX st_adjust value. This needs to be connected to MRMAC IP port ctl_rx_ptp_st_adjust[31:0]
mrmac_rx_ptp_st_adjust_type[1:0] O MRMAC RX st_adjust type. This needs to be connected to MRMAC IP port ctl_rx_ptp_st_adjust_type[1:0]
mrmac_rx_ptp_st_adjust_vld O MRMAC RX st_adjust valid. This needs to be connected to MRMAC IP port ctl_rx_ptp_st_adjust_vld
ctl_mrmac_rx_st_adjust_vld I Tie to 1’b0
ctl_mrmac_rx_st_adjust_type[1:0] I Tie to 2’b00
ctl_mrmac_rx_st_adjust[31:0] I Tie to 32’d0
ctl_mrmac_rx_st_overwrite I Tie to 1’b1
ctl_mrmac_tx_st_adjust_vld I Tie to 1’b0
ctl_mrmac_tx_st_adjust_type[1:0] I Tie to 2’b00
ctl_mrmac_tx_st_adjust[31:0] I Tie to 32’d0
ctl_mrmac_tx_st_overwrite I Tie to 1’b1
tx_period[55:0] I TX period value. Unused and reserved for future enhancement. Tie to 56’d0.
ctl_half_period_adjust[15:0] I Half period Adjust value. Unused and reserved for future enhancement. Tie to 16’d0.
ctl_mrmac_1clk_adjust[15:0] I 1Clock Adjust value. Unused and reserved for future enhancement. Tie to 16’d0.
mrmac_stat_tx_ptp_st_sync I Unused and reserved for future enhancement. Tie to 1’b0.
mrmac_stat_tx_ptp_systemtimer[54:0] I Unused and reserved for future enhancement. Tie to 55’d0.
mrmac_stat_rx_ptp_st_sync I Unused and reserved for future enhancement. Tie to 1’b0.
mrmac_stat_rx_ptp_systemtimer[54:0] I Unused and reserved for future enhancement. Tie to 55’d0.
stat_mrmac_tx_ts_diff_msb[31:0] O Unused and reserved for future enhancement.
stat_mrmac_tx_ts_diff_lsb[31:0] O Unused and reserved for future enhancement.
stat_mrmac_rx_ts_diff_msb[31:0] O Unused and reserved for future enhancement.
stat_mrmac_rx_ts_diff_lsb[31:0] O Unused and reserved for future enhancement.
stat_mrmac_tx_ts_diff_reduced[31:0] O Unused and reserved for future enhancement.
stat_mrmac_rx_ts_diff_reduced[31:0] O Unused and reserved for future enhancement.
Figure 1. SYSTIMER BUS Interface