PTP Port Timer Sub Block - 2.3 English

Versal Devices Integrated 100G Multirate Ethernet MAC Subsystem Product Guide (PG314)

Document ID
PG314
Release Date
2024-05-30
Version
2.3 English

These sub-blocks contain the per port TX and RX timers which are typically clocked by their respective TX and RX PHY clocks (tx_phy_clk and rx_phy_clk). The timer synchronizer IP allows for a maximum of sixteen port timers to be enabled at time of generation.

These port timers maintain time in both the ToD (48-bit seconds and 30-bits nano-sec) and Continuous time/Correction Field (63-bits CF) formats, and provide those outputs synchronized to the tx_phy_clk and rx_phy_clk for use by AMD Ethernet IP.

It is expected that each port’s TX and RX clock domains might be asynchronous with the Master timer’s ts_clk clock. The port timers contain synchronization logic to domain cross the PTP System Timer’s load-pulse and timer update values.

As the PTP System Timer is initialized, or synchronized to the high precision reference clock, it in turn pushes its updated timer value to all the port times which are connected to it. After initialization, the Timer Syncer IP can be configured such that the Port Timers are continuously kept in-sync with the PTP System Timer’s master ToD value, or the Port Timers can be independently controlled.