Normal Transmission - 2.3 English

Versal Devices Integrated 100G Multirate Ethernet MAC Subsystem Product Guide (PG314)

Document ID
PG314
Release Date
2024-05-30
Version
2.3 English

In the following figure a typical sequence of frame transmits are shown. Segments 2 through 4 are not shown to keep the diagram compact.

Figure 1. AXI4-Stream Segmented Transmit Normal Frame Transmission

Here are the highlights of this sequence of operations:

  1. In cycle #4, a new frame (Frame A) is started in Segment 0. Frame A is 62 bytes long (it becomes 66B long after FCS is appended). Segment 0 ENA is asserted along with SOP. The first word of data, A0, appears. Preamble is provided on the tx_preamblein_0 port. The frame continues in Segment 1, 2, 3, 4, and 5.
  2. In cycle #5, frame A continues in Segment 0, but ends in Segment 1 when EOP is asserted. The MTY signal toggles to indicate the number of unused bytes in this segment (3’h2 in this case). A new frame, Frame B, begins in Segment 5 (data = B0). Again, the tx_preamblein_0 provides the preamble.
  3. Frame B continues through cycle #6 across all segments (data B1 through B6).
  4. In cycle #7, Frame B ends in Segment 5 with data B12. EOP is asserted in this segment.
  5. In cycle #8 a new frame, Frame C, is initiated. However, the AXI4-Stream interface has deasserted tx_axis_tready_0. The user logic must hold the inputs until tx_axis_tready_0 is asserted again.
  6. In cycle #9 the tready signal has been asserted again and so the transfer is accepted. Frame C begins in Segment 0 (SOP asserted) and continues through to Segment 5.
  7. Frame C continues in cycle #10, across Segment 0 through 5.
  8. In cycle #11, Frame C ends in Segment 0 with the assertion of EOP. The user logic does not have any more data to send so it keeps ENA deasserted in segments 1 through 5.
  9. In the subsequent cycle, #12, there is no data at all to send and so the user logic deasserts tx_axis_tvalid_0 to indicate that the bus is completely idle.
  10. Finally, in cycle #13, Segment 1, a new frame, Frame D, begins. The user logic asserts tx_axis_tvalid_0 again. Frame D continues through to Segment 5.
  11. Frame D continues in cycle #14 and beyond.