Normal Frame Receive - 2.3 English

Versal Devices Integrated 100G Multirate Ethernet MAC Subsystem Product Guide (PG314)

Document ID
PG314
Release Date
2024-05-30
Version
2.3 English

In the following figure, a typical sequence of frame transmits are shown. As before, Segments 2 through 4 are omitted to keep the diagram compact. This figure depicts the same sequence of events similar to the previous segmented transmit example, but in the receive direction.

Figure 1. AXI4-Stream Segmented Normal Frame Receive

As in the earlier example, Frame A starts in Segment 0 of cycle #4 which terminates with EOF in Segment 1 of cycle #5. Frame B begins in Segment 5 of the same cycle, which ends in Segment 5 of cycle #7.

There is no bus activity in cycle #8, therefore the MRMAC deasserts rx_axis_tvalid_0 for the cycle. A new frame, Frame C, begins in cycle #9 and ends in cycle #11. Cycle #12 is idle (tvalid = 0) and the final frame in this example is transferred starting in cycle #13, Segment #1.