MRMAC Status Ports - 2.3 English

Versal Devices Integrated 100G Multirate Ethernet MAC Subsystem Product Guide (PG314)

Document ID
PG314
Release Date
2024-05-30
Version
2.3 English

In addition to the AXI4-Lite registers and counters, the MRMAC IP provides status flag ports to enable ease of integration into user monitoring and interrupt logic. The following table has a list of the output status flags. All status ports are outputs.

Table 1. MRMAC Status Port Descriptions
Port Name Clock Domain Description
stat_rx01_fec_degraded_ser s_axi_aclk RX FEC Degraded Symbol Error
stat_rx23_fec_degraded_ser s_axi_aclk
stat_tx_local_fault_0 s_axi_aclk A value of 1 indicates the transmit encoder state machine is in the TX_INIT state.
stat_tx_local_fault_1 s_axi_aclk
stat_tx_local_fault_2 s_axi_aclk
stat_tx_local_fault_3 s_axi_aclk
stat_tx_frame_error_0 s_axi_aclk Packets with tx_errin set to indicate an End of Packet (EOP) abort.
stat_tx_frame_error_1 s_axi_aclk
stat_tx_frame_error_2 s_axi_aclk
stat_tx_frame_error_3 s_axi_aclk
stat_tx_tsn_preempted_pkt_0 s_axi_aclk Time-sensitive networking (TSN) preempted packets.
stat_tx_tsn_preempted_pkt_1 s_axi_aclk
stat_tx_tsn_preempted_pkt_2 s_axi_aclk
stat_tx_tsn_preempted_pkt_3 s_axi_aclk
stat_tx_tsn_fragment_0 s_axi_aclk Time-sensitive networking (TSN) fragmented packets.
stat_tx_tsn_fragment_1 s_axi_aclk
stat_tx_tsn_fragment_2 s_axi_aclk
stat_tx_tsn_fragment_3 s_axi_aclk
stat_tx_pause_valid_0[8:0] tx_axi_clk_0 Set to 1 when a pause packet is sent. If Bit[8] is set, it means a global pause packet was transmitted.
stat_tx_pause_valid_1[8:0] tx_axi_clk_0
stat_tx_pause_valid_2[8:0] tx_axi_clk_0, tx_axi_clk_2
stat_tx_pause_valid_3[8:0] tx_axi_clk_0, tx_axi_clk_2
stat_tx_axis_unf_0 s_axi_aclk A value of 1 indicates that the AXI4-Stream interface has experienced an underflow.
stat_tx_axis_unf_1 s_axi_aclk
stat_tx_axis_unf_2 s_axi_aclk
stat_tx_axis_unf_3 s_axi_aclk
stat_tx_axis_err_0 s_axi_aclk A value of 1 indicates that the AXI4-Stream interface has encountered an error.
stat_tx_axis_err_1 s_axi_aclk
stat_tx_axis_err_2 s_axi_aclk
stat_tx_axis_err_3 s_axi_aclk
stat_tx_flexif_err_0 s_axi_aclk A value of 1 indicates that the TX Flex I/F has encountered an error.
stat_tx_flexif_err_1 s_axi_aclk
stat_tx_flexif_err_2 s_axi_aclk
stat_tx_flexif_err_3 s_axi_aclk
stat_tx_pcs_bad_code_0[2:0] s_axi_aclk A value of 1 indicates that bad PCS code was observed.
stat_tx_pcs_bad_code_1[2:0] s_axi_aclk
stat_tx_pcs_bad_code_2[2:0] s_axi_aclk
stat_tx_pcs_bad_code_3[2:0] s_axi_aclk
stat_tx_flex_fifo_ovf_0 s_axi_aclk A value of 1 indicates that the Flex I/F FIFO has overflowed.
stat_tx_flex_fifo_ovf_1 s_axi_aclk
stat_tx_flex_fifo_ovf_2 s_axi_aclk
stat_tx_flex_fifo_ovf_3 s_axi_aclk
stat_tx_flex_fifo_udf_0 s_axi_aclk A value of 1 indicates that the Flex I/F FIFO has underflowed.
stat_tx_flex_fifo_udf_1 s_axi_aclk
stat_tx_flex_fifo_udf_2 s_axi_aclk
stat_tx_flex_fifo_udf_3 s_axi_aclk
stat_tx_bad_fcs_0 s_axi_aclk Total number of packets greater than 64 bytes that have FCS errors.
stat_tx_bad_fcs_1 s_axi_aclk
stat_tx_bad_fcs_2 s_axi_aclk
stat_tx_bad_fcs_3 s_axi_aclk
stat_tx_ecc_err_0[1:0] s_axi_aclk Asserted when any other ECC error is detected.

Indicates an ECC error was detected in the memory for that port.

stat_tx_ecc_err_1[1:0] s_axi_aclk
stat_tx_ecc_err_2[1:0] s_axi_aclk
stat_tx_ecc_err_3[1:0] s_axi_aclk
stat_tx_fec_pcs_lane_align_0 s_axi_aclk Indicates that all the transmit FEC lanes are aligned/deskewed and ready to transmit data.
stat_tx_fec_pcs_lane_align_1 s_axi_aclk
stat_tx_fec_pcs_lane_align_2 s_axi_aclk
stat_tx_fec_pcs_lane_align_3 s_axi_aclk
stat_tx_fec_pcs_block_lock_0[4:0] s_axi_aclk Indicates that the PCS has achieved block lock on the corresponding lanes.
stat_tx_fec_pcs_block_lock_1[4:0] s_axi_aclk
stat_tx_fec_pcs_block_lock_2[4:0] s_axi_aclk
stat_tx_fec_pcs_block_lock_3[4:0] s_axi_aclk
stat_tx_fec_pcs_am_lock_0[4:0] s_axi_aclk Indicates that all of the PCS lanes have achieved Alignment Marker lock.
stat_tx_fec_pcs_am_lock_1[4:0] s_axi_aclk
stat_tx_fec_pcs_am_lock_2[4:0] s_axi_aclk
stat_tx_fec_pcs_am_lock_3[4:0] s_axi_aclk
stat_rx_block_lock_0[19:0] s_axi_aclk Indicates that the PCS has achieved block lock on the corresponding PCS lane as defined by IEEE 802.3. A value of 1 indicates block lock is achieved.
stat_rx_synced_0[19:0] s_axi_aclk Word Boundary Synchronized. Indicates whether the PCS is word boundary synchronized (PCS Lane Marker Word has been detected) on the corresponding PCS lane. Corresponds to MDIO register bit 3.52.7:0 and 3.53.11:0 as defined in Clause 82.3.
stat_rx_synced_err_0[19:0] s_axi_aclk Word Boundary Synchronization Error. Indicates whether an error occurred during the word boundary synchronization on the corresponding PCS lane.
stat_rx_mf_err_0[19:0] s_axi_aclk PCS Lane Marker Word Error. These signals indicate that an incorrectly formed PCS Lane Marker Word was detected in the respective PCS lane. A value of 1 indicates an error occurred.
stat_rx_block_lock_1 s_axi_aclk Indicates that the PCS has achieved block lock on the corresponding PCS lane as defined by IEEE 802.3. A value of 1 indicates block lock is achieved.
stat_rx_block_lock_2[3:0] s_axi_aclk Indicates that the PCS has achieved block lock on the corresponding PCS lane as defined by IEEE 802.3. A value of 1 indicates block lock is achieved.
stat_rx_synced_2[3:0] s_axi_aclk Word Boundary Synchronized. Indicates whether the PCS is word boundary synchronized (PCS Lane Marker Word has been detected) on the corresponding PCS lane.
stat_rx_synced_err_2[3:0] s_axi_aclk Word Boundary Synchronization Error. Indicates whether an error occurred during the word boundary synchronization on the corresponding PCS lane.
stat_rx_mf_err_2[3:0] s_axi_aclk PCS Lane Marker Word Error. These signals indicate that an incorrectly formed PCS Lane Marker Word was detected in the respective PCS lane. A value of 1 indicates an error occurred.
stat_rx_block_lock_3 s_axi_aclk Indicates that the PCS has achieved block lock on the corresponding PCS lane as defined by IEEE 802.3. A value of 1 indicates block lock is achieved.
stat_rx_flexif_err_0 s_axi_aclk A value of 1 indicates that the TX Flex I/F has encountered an error.
stat_rx_flexif_err_1 s_axi_aclk
stat_rx_flexif_err_2 s_axi_aclk
stat_rx_flexif_err_3 s_axi_aclk
stat_rx_pcs_bad_code_0 s_axi_aclk Increment for 64B/66B code violations. This signal indicates that the RX PCS receive state machine is in the RX_E state as specified by the IEEE Std 802.3. This output can be used to generate MDIO register 3.33:7:0 as defined in Clause 82.3.
stat_rx_pcs_bad_code_1 s_axi_aclk
stat_rx_pcs_bad_code_2 s_axi_aclk
stat_rx_pcs_bad_code_3 s_axi_aclk
stat_rx_flex_fifo_ovf_0 s_axi_aclk A valid of 1 indicates that the Flex I/F experienced an overflow.
stat_rx_flex_fifo_ovf_1 s_axi_aclk
stat_rx_flex_fifo_ovf_2 s_axi_aclk
stat_rx_flex_fifo_ovf_3 s_axi_aclk
stat_rx_flex_fifo_udf_0 s_axi_aclk A valid of 1 indicates that the Flex I/F experienced an underflow.
stat_rx_flex_fifo_udf_1 s_axi_aclk
stat_rx_flex_fifo_udf_2 s_axi_aclk
stat_rx_flex_fifo_udf_3 s_axi_aclk
stat_rx_status_0 s_axi_aclk A value of 1 indicates the PCS is aligned and not in hi_ber state. Corresponds to MDIO register bit 3.32.12 as defined in Clause 82.3.
stat_rx_status_1 s_axi_aclk
stat_rx_status_2 s_axi_aclk
stat_rx_status_3 s_axi_aclk
stat_rx_vl_demuxed_0 s_axi_aclk After word boundary synchronization is achieved on each lane. If a bit of this bus is 1, it indicates that the corresponding PCS lane was properly found and de-MUXed.
stat_rx_vl_demuxed_2 s_axi_aclk
stat_rx_lane0_vlm_bip7_valid_0 rx_axi_clk_0 Indicates that the bip7 byte value is valid.
stat_rx_lane0_vlm_bip7_valid_2 rx_axi_clk_0, rx_axi_clk_2
stat_rx_lane0_vlm_bip7_0[7:0] rx_axi_clk_0 This is the received value of the bip7 byte in the PCS lane0 marker.
stat_rx_lane0_vlm_bip7_2[7:0] rx_axi_clk_0, rx_axi_clk_2
stat_rx_aligned_0 s_axi_aclk When stat_rx_aligned is a value of 1, all of the lanes are aligned/deskewed and the receiver is ready to receive packet data.
stat_rx_aligned_2 s_axi_aclk
stat_rx_aligned_err_0 s_axi_aclk When stat_rx_aligned_err is a value of 1, either Lane alignment failed after several attempts, or Lane alignment was lost (stat_rx_aligned was asserted and then it was negated).
stat_rx_aligned_err_2 s_axi_aclk
stat_rx_misaligned_0 s_axi_aclk When stat_rx_misaligned is a value of 1, a valid PCS Lane Marker Word was not received on all PCS lanes simultaneously.
stat_rx_misaligned_2 s_axi_aclk
stat_rx_valid_ctrl_code_0 s_axi_aclk Indicates that a block with a valid control code was received.
stat_rx_valid_ctrl_code_1 s_axi_aclk
stat_rx_valid_ctrl_code_2 s_axi_aclk
stat_rx_valid_ctrl_code_3 s_axi_aclk
stat_rx_hi_ber_0 s_axi_aclk When set to 1, the BER is too high as defined by IEEE Std 802.3. Corresponds to MDIO register bit 3.32.1 as defined in Clause 82.3.
stat_rx_hi_ber_1 s_axi_aclk
stat_rx_hi_ber_2 s_axi_aclk
stat_rx_hi_ber_3 s_axi_aclk
stat_rx_bad_code_0 s_axi_aclk Increment for 64B/66B code violations. This signal indicates that the RX PCS receive state machine is in the RX_E state as specified by the IEEE Std 802.3. This output can be used to generate MDIO register 3.33:7:0 as defined in Clause 82.3.
stat_rx_bad_code_1 s_axi_aclk
stat_rx_bad_code_2 s_axi_aclk
stat_rx_bad_code_3 s_axi_aclk
stat_rx_bad_preamble_0 s_axi_aclk This signal indicates if the Ethernet packet received was preceded by a valid preamble. A value of 1 indicates that an invalid preamble was received.
stat_rx_bad_preamble_1 s_axi_aclk
stat_rx_bad_preamble_2 s_axi_aclk
stat_rx_bad_preamble_3 s_axi_aclk
stat_rx_bad_sfd_0 s_axi_aclk Increment bad start of frame delimiter (SFD). This signal indicates if the Ethernet packet received was preceded by a valid SFD. A value of 1 indicates that an invalid SFD was received.
stat_rx_bad_sfd_1 s_axi_aclk
stat_rx_bad_sfd_2 s_axi_aclk
stat_rx_bad_sfd_3 s_axi_aclk
stat_rx_got_signal_os_0 s_axi_aclk Indicates that a Signal Ordered Set was received.
stat_rx_got_signal_os_1 s_axi_aclk
stat_rx_got_signal_os_2 s_axi_aclk
stat_rx_got_signal_os_3 s_axi_aclk
stat_rx_invalid_start_0 s_axi_aclk Indicates that a Start code has been detected, but has been invalidated potentially leading to a packet not being recognized. A Start code is invalidated if it immediately follows an Error code, or if it is not preceded by sufficient IPG.
stat_rx_invalid_start_1 s_axi_aclk
stat_rx_invalid_start_2 s_axi_aclk
stat_rx_invalid_start_3 s_axi_aclk
stat_rx_test_pattern_mismatch_0 s_axi_aclk Total number of test pattern mismatches.
stat_rx_test_pattern_mismatch_1 s_axi_aclk
stat_rx_test_pattern_mismatch_2 s_axi_aclk
stat_rx_test_pattern_mismatch_3 s_axi_aclk
stat_rx_local_fault_0 s_axi_aclk

This output is High when stat_rx_internal_local_fault or stat_rx_received_local_fault is asserted.

stat_rx_local_fault_1 s_axi_aclk
stat_rx_local_fault_2 s_axi_aclk
stat_rx_local_fault_3 s_axi_aclk
stat_rx_internal_local_fault_0 s_axi_aclk If this bit is sampled as a 1, it indicates a remote fault condition was detected. If this bit is sampled as a 0, a remote fault condition does not exist.
stat_rx_internal_local_fault_1 s_axi_aclk
stat_rx_internal_local_fault_2 s_axi_aclk
stat_rx_internal_local_fault_3 s_axi_aclk
stat_rx_received_local_fault_0 s_axi_aclk This signal goes High when enough local fault words are received from the link partner to trigger a fault condition as specified by the IEEE fault state machine.
stat_rx_received_local_fault_1 s_axi_aclk
stat_rx_received_local_fault_2 s_axi_aclk
stat_rx_received_local_fault_3 s_axi_aclk
stat_rx_remote_fault_0 s_axi_aclk If this bit is sampled as a 1, it indicates a remote fault condition was detected. If this bit is sampled as a 0, a remote fault condition does not exist.
stat_rx_remote_fault_1 s_axi_aclk
stat_rx_remote_fault_2 s_axi_aclk
stat_rx_remote_fault_3 s_axi_aclk
stat_rx_truncated_0 s_axi_aclk Indicates RX frames that were truncated due to their length exceeding the defined maximum length.
stat_rx_truncated_1 s_axi_aclk
stat_rx_truncated_2 s_axi_aclk
stat_rx_truncated_3 s_axi_aclk
stat_rx_pause_valid_0[8:0] rx_axi_clk_0 RX Pause Valid

Each bit of stat_rx_pause_valid_N[8:0] is associated with a pause priority (Bit[8] is for global pause signaling).

stat_rx_pause_valid_1[8:0] rx_axi_clk_0
stat_rx_pause_valid_2[8:0] rx_axi_clk_0, rx_axi_clk_2
stat_rx_pause_valid_3[8:0] rx_axi_clk_0, rx_axi_clk_2
stat_rx_pause_quanta0_0[15:0] rx_axi_clk_0 These buses indicate the quanta received for each of the eight priorities in priority-based pause operation and the global pause operation. The value for stat_rx_pause_quanta[8] is used for global pause operation. All other values are used for priority pause operation.
stat_rx_pause_quanta0_1[15:0] rx_axi_clk_0
stat_rx_pause_quanta0_2[15:0] rx_axi_clk_0, rx_axi_clk_2
stat_rx_pause_quanta0_3[15:0] rx_axi_clk_0, rx_axi_clk_2
stat_rx_pause_quanta1_0[15:0] rx_axi_clk_0 These buses indicate the quanta received for each of the eight priorities in priority-based pause operation and the global pause operation. The value for stat_rx_pause_quanta[8] is used for global pause operation. All other values are used for priority pause operation.
stat_rx_pause_quanta1_1[15:0] rx_axi_clk_0
stat_rx_pause_quanta1_2[15:0] rx_axi_clk_0, rx_axi_clk_2
stat_rx_pause_quanta1_3[15:0] rx_axi_clk_0, rx_axi_clk_2
stat_rx_pause_quanta2_0[15:0] rx_axi_clk_0 These buses indicate the quanta received for each of the eight priorities in priority-based pause operation and the global pause operation. The value for stat_rx_pause_quanta[8] is used for global pause operation. All other values are used for priority pause operation.
stat_rx_pause_quanta2_1[15:0] rx_axi_clk_0
stat_rx_pause_quanta2_2[15:0] rx_axi_clk_0, rx_axi_clk_2
stat_rx_pause_quanta2_3[15:0] rx_axi_clk_0, rx_axi_clk_2
stat_rx_pause_quanta3_0[15:0] rx_axi_clk_0 These buses indicate the quanta received for each of the eight priorities in priority-based pause operation and the global pause operation. The value for stat_rx_pause_quanta[8] is used for global pause operation. All other values are used for priority pause operation.
stat_rx_pause_quanta3_1[15:0] rx_axi_clk_0
stat_rx_pause_quanta3_2[15:0] rx_axi_clk_0, rx_axi_clk_2
stat_rx_pause_quanta3_3[15:0] rx_axi_clk_0, rx_axi_clk_2
stat_rx_pause_quanta4_0[15:0] rx_axi_clk_0 These buses indicate the quanta received for each of the eight priorities in priority-based pause operation and the global pause operation. The value for stat_rx_pause_quanta[8] is used for global pause operation. All other values are used for priority pause operation.
stat_rx_pause_quanta4_1[15:0] rx_axi_clk_0
stat_rx_pause_quanta4_2[15:0] rx_axi_clk_0, rx_axi_clk_2
stat_rx_pause_quanta4_3[15:0] rx_axi_clk_0, rx_axi_clk_2
stat_rx_pause_quanta5_0[15:0] rx_axi_clk_0 These buses indicate the quanta received for each of the eight priorities in priority-based pause operation and the global pause operation. The value for stat_rx_pause_quanta[8] is used for global pause operation. All other values are used for priority pause operation.
stat_rx_pause_quanta5_1[15:0] rx_axi_clk_0
stat_rx_pause_quanta5_2[15:0] rx_axi_clk_0, rx_axi_clk_2
stat_rx_pause_quanta5_3[15:0] rx_axi_clk_0, rx_axi_clk_2
stat_rx_pause_quanta6_0[15:0] rx_axi_clk_0 These buses indicate the quanta received for each of the eight priorities in priority-based pause operation and the global pause operation. The value for stat_rx_pause_quanta[8] is used for global pause operation. All other values are used for priority pause operation.
stat_rx_pause_quanta6_1[15:0] rx_axi_clk_0
stat_rx_pause_quanta6_2[15:0] rx_axi_clk_0, rx_axi_clk_2
stat_rx_pause_quanta6_3[15:0] rx_axi_clk_0, rx_axi_clk_2
stat_rx_pause_quanta7_0[15:0] rx_axi_clk_0 These buses indicate the quanta received for each of the eight priorities in priority-based pause operation and the global pause operation. The value for stat_rx_pause_quanta[8] is used for global pause operation. All other values are used for priority pause operation.
stat_rx_pause_quanta7_1[15:0] rx_axi_clk_0
stat_rx_pause_quanta7_2[15:0] rx_axi_clk_0, rx_axi_clk_2
stat_rx_pause_quanta7_3[15:0] rx_axi_clk_0, rx_axi_clk_2
stat_rx_pause_quanta8_0[15:0] rx_axi_clk_0 These buses indicate the quanta received for each of the eight priorities in priority-based pause operation and the global pause operation. The value for stat_rx_pause_quanta[8] is used for global pause operation. All other values are used for priority pause operation.
stat_rx_pause_quanta8_1[15:0] rx_axi_clk_0
stat_rx_pause_quanta8_2[15:0] rx_axi_clk_0, rx_axi_clk_2
stat_rx_pause_quanta8_3[15:0] rx_axi_clk_0, rx_axi_clk_2
stat_rx_pause_req_0[8:0] rx_axi_clk_0 RX Pause Request

Each bit of stat_rx_pause_req_N[8:0] is associated with a pause priority (Bit[8] is for global pause signaling).

stat_rx_pause_req_1[8:0] rx_axi_clk_0
stat_rx_pause_req_2[8:0] rx_axi_clk_0, rx_axi_clk_2
stat_rx_pause_req_3[8:0] rx_axi_clk_0, rx_axi_clk_2
stat_rx_axis_fifo_overflow_0 s_axi_aclk A value of 1 indicates that the AXI4-Stream interface has experienced an overflow.
stat_rx_axis_fifo_overflow_1 s_axi_aclk
stat_rx_axis_fifo_overflow_2 s_axi_aclk
stat_rx_axis_fifo_overflow_3 s_axi_aclk
stat_rx_axis_err_0 s_axi_aclk A value of 1 indicates that the AXI4-Stream interface has experienced an error.
stat_rx_axis_err_1 s_axi_aclk
stat_rx_axis_err_2 s_axi_aclk
stat_rx_axis_err_3 s_axi_aclk
stat_rx_ecc_err_0[1:0] s_axi_aclk Asserted when any other ECC error is detected.

Indicates that an ECC error was detected on the RX of a given port.

stat_rx_ecc_err_1[1:0] s_axi_aclk
stat_rx_ecc_err_2[1:0] s_axi_aclk
stat_rx_ecc_err_3[1:0] s_axi_aclk
stat_rx_bad_fcs_0 s_axi_aclk Packets received with bad (but not stomped) FCS. A stomped FCS is defined as the bitwise inverse of a good FCS.
stat_rx_bad_fcs_1 s_axi_aclk
stat_rx_bad_fcs_2 s_axi_aclk
stat_rx_bad_fcs_3 s_axi_aclk
stat_rx_tsn_preempted_pkt_0 s_axi_aclk Packets received with TSN preempted packets.
stat_rx_tsn_preempted_pkt_1 s_axi_aclk
stat_rx_tsn_preempted_pkt_2 s_axi_aclk
stat_rx_tsn_preempted_pkt_3 s_axi_aclk
stat_rx_tsn_fragment_0 s_axi_aclk Packets received with TSN fragmented packets.
stat_rx_tsn_fragment_1 s_axi_aclk
stat_rx_tsn_fragment_2 s_axi_aclk
stat_rx_tsn_fragment_3 s_axi_aclk
stat_rx_fec_hi_ser_0 s_axi_aclk Indicates that the number of symbol errors in a 8192-codeword window has exceeded the threshold K (417).
stat_rx_fec_hi_ser_1 s_axi_aclk
stat_rx_fec_hi_ser_2 s_axi_aclk
stat_rx_fec_hi_ser_3 s_axi_aclk
stat_rx_fec_lane_lock_0[3:0] s_axi_aclk Indicates that the FEC has achieved lane lock on the indicated lane.
stat_rx_fec_lane_lock_1 s_axi_aclk
stat_rx_fec_lane_lock_2[3:0] s_axi_aclk
stat_rx_fec_lane_lock_3 s_axi_aclk
stat_rx_fec_corrected_cw_0_0 rx_axi_clk_0 Count of corrected codewords on FEC lane 0.
stat_rx_fec_corrected_cw_0_1 rx_axi_clk_0 Count of corrected codewords on FEC lane 1.
stat_rx_fec_corrected_cw_0_2 rx_axi_clk_0 Count of corrected codewords on FEC lane 2.
stat_rx_fec_corrected_cw_0_3 rx_axi_clk_0 Count of corrected codewords on FEC lane 3.
stat_rx_fec_uncorrected_cw_0_0 rx_axi_clk_0 Count of uncorrected codewords on FEC lane 0.
stat_rx_fec_uncorrected_cw_0_1 rx_axi_clk_0 Count of uncorrected codewords on FEC lane 1.
stat_rx_fec_uncorrected_cw_0_2 rx_axi_clk_0 Count of uncorrected codewords on FEC lane 2.
stat_rx_fec_uncorrected_cw_0_3 rx_axi_clk_0 Count of uncorrected codewords on FEC lane 3.
stat_rx_fec_cw_0_0 rx_axi_clk_0 Count of processed codewords on FEC lane 0.
stat_rx_fec_cw_0_1 rx_axi_clk_0 Count of processed codewords on FEC lane 1.
stat_rx_fec_cw_0_2 rx_axi_clk_0 Count of processed codewords on FEC lane 2.
stat_rx_fec_cw_0_3 rx_axi_clk_0 Count of processed codewords on FEC lane 3.
stat_rx_fec_err_count_0_0[3:0] rx_axi_clk_0 Count of FEC symbol errors on FEC lane 0.
stat_rx_fec_err_count_0_1[3:0] rx_axi_clk_0 Count of FEC symbol errors on FEC lane 1.
stat_rx_fec_err_count_0_2[3:0] rx_axi_clk_0 Count of FEC symbol errors on FEC lane 2.
stat_rx_fec_err_count_0_3[3:0] rx_axi_clk_0 Count of FEC symbol errors on FEC lane 3.
stat_rx_fec_corrected_cw_1 rx_axi_clk_0 Count of corrected codewords on FEC.
stat_rx_fec_uncorrected_cw_1 rx_axi_clk_0 Count of uncorrected codewords on FEC.
stat_rx_fec_cw_1 rx_axi_clk_0 Count of processed codewords on FEC.
stat_rx_fec_err_count_1[3:0] rx_axi_clk_0 Count of FEC symbol errors.
stat_rx_fec_corrected_cw_2_0 rx_axi_clk_0, rx_axi_clk_2 Count of corrected codewords on FEC lane 0.
stat_rx_fec_corrected_cw_2_1 rx_axi_clk_0, rx_axi_clk_2 Count of corrected codewords on FEC lane 1.
stat_rx_fec_corrected_cw_2_2 rx_axi_clk_0, rx_axi_clk_2 Count of corrected codewords on FEC lane 2.
stat_rx_fec_corrected_cw_2_3 rx_axi_clk_0, rx_axi_clk_2 Count of corrected codewords on FEC lane 3.
stat_rx_fec_uncorrected_cw_2_0 rx_axi_clk_0, rx_axi_clk_2 Count of corrected codewords on FEC lane 0.
stat_rx_fec_uncorrected_cw_2_1 rx_axi_clk_0, rx_axi_clk_2 Count of corrected codewords on FEC lane 1.
stat_rx_fec_uncorrected_cw_2_2 rx_axi_clk_0, rx_axi_clk_2 Count of corrected codewords on FEC lane 2.
stat_rx_fec_uncorrected_cw_2_3 rx_axi_clk_0, rx_axi_clk_2 Count of corrected codewords on FEC lane 3.
stat_rx_fec_cw_2_0 rx_axi_clk_0, rx_axi_clk_2 Count of processed codewords on FEC lane 0.
stat_rx_fec_cw_2_1 rx_axi_clk_0, rx_axi_clk_2 Count of processed codewords on FEC lane 1.
stat_rx_fec_cw_2_2 rx_axi_clk_0, rx_axi_clk_2 Count of processed codewords on FEC lane 2.
stat_rx_fec_cw_2_3 rx_axi_clk_0, rx_axi_clk_2 Count of processed codewords on FEC lane 3.
stat_rx_fec_err_count_2_0[3:0] rx_axi_clk_0, rx_axi_clk_2 Count of FEC symbol errors.
stat_rx_fec_err_count_2_1[3:0] rx_axi_clk_0, rx_axi_clk_2 Count of FEC symbol errors.
stat_rx_fec_corrected_cw_3 rx_axi_clk_0, rx_axi_clk_2 Count of corrected codewords on FEC.
stat_rx_fec_uncorrected_cw_3 rx_axi_clk_0, rx_axi_clk_2 Count of uncorrected codewords on FEC.
stat_rx_fec_cw_3 rx_axi_clk_0, rx_axi_clk_2 Count of processed codewords on FEC.
stat_rx_fec_err_count_3[3:0] rx_axi_clk_0, rx_axi_clk_2 Count of FEC symbol errors.
stat_rx_fec_aligned_0 s_axi_aclk Indicates that the FEC is aligned/deskewed and ready to receive packet data.
stat_rx_fec_aligned_1 s_axi_aclk
stat_rx_fec_aligned_2 s_axi_aclk
stat_rx_fec_aligned_3 s_axi_aclk
stat_rx_fec_mapping_0[1:0] s_axi_aclk The number corresponding to the detected lane on Lane 0.
stat_rx_fec_mapping_1[1:0] s_axi_aclk The number corresponding to the detected lane on Lane 1.
stat_rx_fec_mapping_2[1:0] s_axi_aclk The number corresponding to the detected lane on Lane 2.
stat_rx_fec_mapping_3[1:0] s_axi_aclk The number corresponding to the detected lane on Lane 3.
stat_rx_fec_delay_0[14:0] rx_axi_clk_0 The instantaneous delay that has been applied to each of the SerDes lanes in the alignment and deskew block.
stat_rx_framing_err_0[19:0] s_axi_aclk Indicates a sync header error detected.
stat_rx_bip_err_0[19:0] s_axi_aclk BIP8 error indicator for PCS lane 0. A non-zero value indicates the BIP8 signature was in error.
stat_rx_fec_delay_1[14:0] rx_axi_clk_0 The instantaneous delay that has been applied to each of the SerDes lanes in the alignment and deskew block.
stat_rx_framing_err_1 s_axi_aclk Indicates a sync header error detected.
stat_rx_fec_delay_2[14:0] rx_axi_clk_0, rx_axi_clk_2 The instantaneous delay that has been applied to each of the SerDes lanes in the alignment and deskew block.
stat_rx_framing_err_2[3:0] s_axi_aclk Indicates a sync header error detected.
stat_rx_bip_err_2[3:0] s_axi_aclk BIP8 error indicator for PCS lane 0. A non-zero value indicates the BIP8 signature was in error.
stat_rx_fec_delay_3[14:0] rx_axi_clk_0, rx_axi_clk_2 The instantaneous delay that has been applied to each of the SerDes lanes in the alignment and deskew block.
stat_rx_framing_err_3 s_axi_aclk Indicates a sync header error detected.
stat_rx_cl49_82_convert_err_0 rx_axi_clk_0 Port 0 RX CL49_82 convert error
stat_rx_cl49_82_convert_err_1 rx_axi_clk_0 Port 1 RX CL49_82 convert error
stat_rx_cl49_82_convert_err_2

rx_axi_clk_0,

rx_axi_clk_2

Port 2 RX CL49_82 convert error
stat_rx_cl49_82_convert_err_3

rx_axi_clk_0,

rx_axi_clk_2

Port 3 RX CL49_82 convert error
stat_tx_cl49_82_convert_err_0 tx_axi_clk_0 Port 0 TX CL49_82 convert error
stat_tx_cl49_82_convert_err_1 tx_axi_clk_0 Port 1 TX CL49_82 convert error
stat_tx_cl49_82_convert_err_2

tx_axi_clk_0,

tx_axi_clk_2

Port 2 TX CL49_82 convert error
stat_tx_cl49_82_convert_err_3

tx_axi_clk_0,

tx_axi_clk_2

Port 3 TX CL49_82 convert error
stat_rx_flex_mon_fifo_ovf_0 s_axi_aclk Port 0 RX Flex mon fifo overflow
stat_rx_flex_mon_fifo_ovf_1 s_axi_aclk Port 1 RX Flex mon fifo overflow
stat_rx_flex_mon_fifo_ovf_2 s_axi_aclk Port 2 RX Flex mon fifo overflow
stat_rx_flex_mon_fifo_ovf_3 s_axi_aclk Port 3 RX Flex mon fifo overflow
stat_rx_flex_mon_fifo_udf_0 s_axi_aclk Port 0 RX Flex mon fifo underrflow
stat_rx_flex_mon_fifo_udf_1 s_axi_aclk Port 1 RX Flex mon fifo underrflow
stat_rx_flex_mon_fifo_udf_2 s_axi_aclk Port 2 RX Flex mon fifo underrflow
stat_rx_flex_mon_fifo_udf_3 s_axi_aclk Port 3 RX Flex mon fifo underrflow