In the MRMAC PCS Only example design, the MRMAC and GT Quad Base IP are connected along with the MBUFG_GTs. For more information on the GT Quad Base IP, refer to the Versal Adaptive SoC Transceivers Wizard LogiCORE IP Product Guide (PG331).
The MRMAC PCS Only example design simulation uses a block RAM based packet generator and monitor to generate and check Ethernet traffic. A test bench controls and monitors the packet generator and also configures the MRMAC IP through an AXI4-Lite interface.
Note: The MRMAC PCS Only configuration example design only supports
simulation.