MRMAC Memory Map - 2.3 English

Versal Devices Integrated 100G Multirate Ethernet MAC Subsystem Product Guide (PG314)

Document ID
PG314
Release Date
2024-05-30
Version
2.3 English
The AXI4-Lite interface enables access to the MRMAC configuration and statistics registers. Each port has a set of independent Configuration registers, Status registers, and Statistics counters.
Table 1. MRMAC Memory Map
Port Base Address Region
N/A 0x0000 Revision Registers
0 0x0004 Configuration Registers
0x0740 Status Registers and Statistics Counters
1 0x1004 Configuration Registers
0x1740 Status Registers and Statistics Counters
2 0x2004 Configuration Registers
0x2740 Status Registers and Statistics Counters
3 0x3004 Configuration Registers
0x3740 Status Registers and Statistics Counters