MRMAC Control Ports - 2.3 English

Versal Devices Integrated 100G Multirate Ethernet MAC Subsystem Product Guide (PG314)

Document ID
PG314
Release Date
2024-05-30
Version
2.3 English

In addition to the AXI4-Lite configuration registers, the MRMAC IP requires some control inputs illustrated in the following table. All control ports are inputs.

Table 1. MRMAC Control Port Descriptions
Port Name Clock Domain Description
ctl_rx_fec_fc32_ra_mode_0 s_axi_aclk RX_RESET needed after change to CTL_RX_FEC_FC32_RA_MODE_*.
ctl_rx_fec_fc32_ra_mode_1
ctl_rx_fec_fc32_ra_mode_2
ctl_rx_fec_fc32_ra_mode_3
ctl_rx_pause_ack_0[8:0] rx_axi_clk[0] RX Pause Processing Acknowledge

Each bit of ctl_rx_pause_ack_N[8:0] is associated with a pause priority (Bit[8] is for global pause signaling).

ctl_rx_pause_ack_1[8:0]
ctl_rx_pause_ack_2[8:0] rx_axi_clk[1]
ctl_rx_pause_ack_3[8:0]
ctl_rx_pause_enable_0[8:0] rx_axi_clk[0] RX Pause Packet Enable

Each bit of ctl_rx_pause_enable_N[8:0] is associated with a pause priority (Bit[8] is for global pause signaling).

ctl_rx_pause_enable_1[8:0]
ctl_rx_pause_enable_2[8:0] rx_axi_clk[1]
ctl_rx_pause_enable_3[8:0]
ctl_rx_ptp_st_adjust_0[31:0] rx_ts_clk[0] Specifies System Timer Adjust
ctl_rx_ptp_st_adjust_1[31:0] rx_ts_clk[1]
ctl_rx_ptp_st_adjust_2[31:0] rx_ts_clk[2]
ctl_rx_ptp_st_adjust_3[31:0] rx_ts_clk[3]
ctl_rx_ptp_st_adjust_type_0[1:0] rx_ts_clk[0] Specifies the desired System Timer Adjustment Type
ctl_rx_ptp_st_adjust_type_1[1:0] rx_ts_clk[1]
ctl_rx_ptp_st_adjust_type_2[1:0] rx_ts_clk[2]
ctl_rx_ptp_st_adjust_type_3[1:0] rx_ts_clk[3]
ctl_rx_ptp_st_adjust_vld_0 rx_ts_clk[0] Specifies the System Timer Adjust is valid.
ctl_rx_ptp_st_adjust_vld_1 rx_ts_clk[1]
ctl_rx_ptp_st_adjust_vld_2 rx_ts_clk[2]
ctl_rx_ptp_st_adjust_vld_3 rx_ts_clk[3]
ctl_rx_ptp_st_overwrite_0 rx_ts_clk[0] System Timer Overwrite
ctl_rx_ptp_st_overwrite_1 rx_ts_clk[1]
ctl_rx_ptp_st_overwrite_2 rx_ts_clk[2]
ctl_rx_ptp_st_overwrite_3 rx_ts_clk[3]
ctl_rx_ptp_st_sync_0 rx_ts_clk[0] System Timer Sync
ctl_rx_ptp_st_sync_1 rx_ts_clk[1]
ctl_rx_ptp_st_sync_2 rx_ts_clk[2]
ctl_rx_ptp_st_sync_3 rx_ts_clk[3]
ctl_rx_ptp_systemtimer_0[54:0] rx_ts_clk[0] System timer input in units of 2-8 nanoseconds (unsigned). This field maps to Bits[62:8] of the correction field format in IEEE 1588-2008 (with the bottom 8 bits set to 0).
ctl_rx_ptp_systemtimer_1[54:0] rx_ts_clk[1]
ctl_rx_ptp_systemtimer_2[54:0] rx_ts_clk[2]
ctl_rx_ptp_systemtimer_3[54:0] rx_ts_clk[3]
ctl_tx_lane0_vlm_bip7_override_01 tx_axi_clk[0] Indicates that the bip7 byte value is overridden.
ctl_tx_lane0_vlm_bip7_override_23 tx_axi_clk[1]
ctl_tx_lane0_vlm_bip7_override_value_01[7:0] tx_axi_clk[0] Indicates that the bip7 byte value has a override value.
ctl_tx_lane0_vlm_bip7_override_value_23[7:0] tx_axi_clk[1]
ctl_tx_pause_req_0[8:0] tx_axi_clk[0] TX Pause Request

Each bit of ctl_tx_pause_req_N[8:0] is associated with a pause priority (Bit[8] is for global pause signaling).

ctl_tx_pause_req_1[8:0] tx_axi_clk[0]
ctl_tx_pause_req_2[8:0] tx_axi_clk[1]
ctl_tx_pause_req_3[8:0] tx_axi_clk[1]
ctl_tx_ptp_st_adjust_0[31:0] tx_ts_clk[0] Specifies System Timer Adjust
ctl_tx_ptp_st_adjust_1[31:0] tx_ts_clk[1]
ctl_tx_ptp_st_adjust_2[31:0] tx_ts_clk[2]
ctl_tx_ptp_st_adjust_3[31:0] tx_ts_clk[3]
ctl_tx_ptp_st_adjust_type_0[1:0] tx_ts_clk[0] Specifies the desired System Timer Adjustment Type
ctl_tx_ptp_st_adjust_type_1[1:0] tx_ts_clk[1]
ctl_tx_ptp_st_adjust_type_2[1:0] tx_ts_clk[2]
ctl_tx_ptp_st_adjust_type_3[1:0] tx_ts_clk[3]
ctl_tx_ptp_st_adjust_vld_0 tx_ts_clk[0] Specifies the System Timer Adjust is valid.
ctl_tx_ptp_st_adjust_vld_1 tx_ts_clk[1]
ctl_tx_ptp_st_adjust_vld_2 tx_ts_clk[2]
ctl_tx_ptp_st_adjust_vld_3 tx_ts_clk[3]
ctl_tx_ptp_st_overwrite_0 tx_ts_clk[0] System Timer Overwrite
ctl_tx_ptp_st_overwrite_1 tx_ts_clk[1]
ctl_tx_ptp_st_overwrite_2 tx_ts_clk[2]
ctl_tx_ptp_st_overwrite_3 tx_ts_clk[3]
ctl_tx_ptp_st_sync_0 tx_ts_clk[0] System Timer Sync
ctl_tx_ptp_st_sync_1 tx_ts_clk[1]
ctl_tx_ptp_st_sync_2 tx_ts_clk[2]
ctl_tx_ptp_st_sync_3 tx_ts_clk[3]
ctl_tx_ptp_systemtimer_0[54:0] tx_ts_clk[0] System timer input in units of 2-8 nanoseconds (unsigned). This field maps to Bits[62:8] of the correction field format in IEEE 1588-2008 (with the bottom 8 bits set to 0).
ctl_tx_ptp_systemtimer_1[54:0] tx_ts_clk[1]
ctl_tx_ptp_systemtimer_2[54:0] tx_ts_clk[2]
ctl_tx_ptp_systemtimer_3[54:0] tx_ts_clk[3]
ctl_tx_resend_pause_0 Asynchronous Transmit Resend Pause
ctl_tx_resend_pause_1
ctl_tx_resend_pause_2
ctl_tx_resend_pause_3
ctl_tx_send_idle_0 Asynchronous

(Parameter) 1

Transmit Idle code words. If this input is sampled as a 1, the TX path only transmits Idle code words. This input should be set to 1 when the partner device is sending Remote Fault Indication (RFI) code words.
ctl_tx_send_idle_1
ctl_tx_send_idle_2
ctl_tx_send_idle_3
ctl_tx_send_idle_in_0 Asynchronous

(Physical Port) 1

Transmit Send Idle Code Words Input
ctl_tx_send_idle_in_1
ctl_tx_send_idle_in_2
ctl_tx_send_idle_in_3
ctl_tx_send_lfi_0 Asynchronous

(Parameter) 1

Transmit Local Fault Indication (LFI) code word. Takes precedence over RFI.
ctl_tx_send_lfi_1
ctl_tx_send_lfi_2
ctl_tx_send_lfi_3
ctl_tx_send_lfi_in_0 Asynchronous

(Physical Port) 1

Transmit Send Local Fault Indication Input
ctl_tx_send_lfi_in_1
ctl_tx_send_lfi_in_2
ctl_tx_send_lfi_in_3
ctl_tx_send_rfi_0 Asynchronous

(Parameter) 1

Transmit Remote Fault Indication (RFI) code word. If this input is sampled as a 1, the TX path only transmits Remote Fault code words. This input should be set to 1 until the RX path is fully aligned and is ready to accept data from the link partner.
ctl_tx_send_rfi_1
ctl_tx_send_rfi_2
ctl_tx_send_rfi_3
ctl_tx_send_rfi_in_0 Asynchronous

(Physical Port) 1

Transmit Send Remote Fault Indication Input
ctl_tx_send_rfi_in_1
ctl_tx_send_rfi_in_2
ctl_tx_send_rfi_in_3
  1. User can either set the parameter or set the value physically at the port. Both will have same effect on IP. Physical port can be changed dynamically , but parameter can be set only during IP Generation.