Internal Sub-Block Ports - 2.3 English

Versal Devices Integrated 100G Multirate Ethernet MAC Subsystem Product Guide (PG314)

Document ID
PG314
Release Date
2024-05-30
Version
2.3 English

The following tables contain select ports present on the IP sub-blocks to assist in debugging.

Table 1. Internal Sub-Block Ports
Signal Direction Clock Domain Description
External ToD Bus Ports
ext_tod_bus_sec OUT ts_clk

Seconds value sent to PTP System Timer

ext_tod_bus_ns

OUT ts_clk

Nanoseconds value sent to PTP System Timer

ext_tod_bus_1pps

OUT ts_clk 1PPS sent to PTP System Timer
PTP System Timer Ports

sys_tod_sec[48:0]

OUT ts_clk

System Timer ToD seconds field.

sys_tod_ns[31:0]

OUT ts_clk

System Timer ToD nano-seconds field.

sys_tod_corr[63:0]

OUT ts_clk

System Timer ToD CF format.

update_timer OUT ts_clk

Sync update pulse to the Port Timer Blocks.

Asserted when the Master timer is synchronized either by the Ext ToD I/F or via register updates

sys_timer_1pps_out OUT ts_clk

1-PPS output to External ToD Bus Block.

This port is asserted when the System Timer’s nano-second field rolls-over.

Port Timer Ports

update_port_timer

IN ts_clk

Sync update pulse driven by the System Timer

sys_tod_sec_in[48:0]

IN ts_clk

System Timer seconds field.

Present only when the Timer Format is ToD or Both

sys_tod_ns_in[31:0]

IN ts_clk

System Timer nano-seconds field.

Present only when the Timer Format is ToD or Both

sys_tod_corr_in[63:0]

IN ts_clk

System Timer CF field.

Present only when the Timer Format is CF or Both