|
Subsystem Specifics |
| Supported Device Family
(1)
|
AMD Versal™
architecture |
| Supported User Interfaces |
AXI4-Stream, AXI4-Lite
|
| Resources |
Performance and Resource Utilization
|
| Provided with
Subsystem
|
| Design Files |
Encrypted RTL |
| Example Design |
Verilog |
| Test Bench |
Verilog |
| Constraints File |
Xilinx Design Constraints (XDC) |
| Simulation Model |
Verilog |
| Supported S/W Driver |
Linux Kernel. The drivers for 10G and 25GE are available here. |
| Tested Design Flows
(2)
|
| Design Entry |
AMD Vivado™ Design Suite
|
| Simulation |
For supported simulators, see the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973). |
| Synthesis |
Synopsys or Vivado synthesis |
| Support |
| Release Notes and Known Issues |
Master Answer Record: 75817
|
| All Vivado IP Change
Logs |
Master Vivado IP
Change Logs: 72775
|
|
Support web page
|
- For a complete list of supported devices, see
the Vivado IP catalog.
- For the supported versions of the tools, see
the
Vivado Design Suite User Guide: Release
Notes, Installation, and Licensing (UG973).
|