GT Quad Transceiver (SerDes) Modes - 2.3 English

Versal Devices Integrated 100G Multirate Ethernet MAC Subsystem Product Guide (PG314)

Document ID
PG314
Release Date
2024-05-30
Version
2.3 English

The MRMAC is capable of interfacing with the AMD Versalâ„¢ GTY transceivers through the programmable logic region. Each GT Quad lane has a dedicated transceiver interface on the MRMAC IP subsystem.

The MRMAC has PCS/PMA lane logic functions including gearbox, scrambling, lane alignment, and lane deskew. For this reason, the transceivers connected to the MRMAC must be configured to operate in RAW mode. The default transceiver lane interface configuration is 16b RAW interface for 10.3125 Gb/s lane logic, 40b RAW interface for 25.78/26.56 Gb/s lane logic, and 80b RAW interface for 53.125 Gb/s lane logic.

For multi-lane PMD lane data rates (such as 100GE or 40GE), the MRMAC GT Quad interface can support per-lane GT Quad recovered clocks in the RX direction. This option reduces transceiver latency and improves 1588 timestamping accuracy at the cost of requiring per-lane FPGA clocking resources.

For designs desiring to reduce the clocking resources consumed by the MRMAC link, the IP also supports having the transceivers configured with per-lane deskew buffering enabled, allowing all RX PMD lanes to share a common master lane clock.

The following table shows a list of all the MRMAC supported interface options for GTY transceivers including the associated line rates, GT datapath width, clock frequency, and the corresponding ctl_serdes_width field setting. The ctl_serdes_width setting is found in the MODE_REG register for each port.

Table 1. GT Quad Operating Modes
MRMAC Operating Mode GT Lane Line Rate (Gb/s) GT Interface Data Width (bits) GT Interface Clock (MHz) ctl_serdes_width [2:0] GT Mode NRZ/PAM4
10GE Narrow 10.3125 16 644.5313 b000 NRZ
10GE Wide 10.3125 32 322.2656 b100 NRZ
25GE Narrow 25.78125 40 644.5313 b010 NRZ
25GE Wide 25.78125 80 322.2656 b110 NRZ
40GE XLAUI-4 Narrow 10.3125 16 644.5313 b000 NRZ
40GE XLAUI-4 Wide 10.3125 32 322.2656 b100 NRZ
50GE 50GAUI-2 (KP4 FEC) Narrow 26.5625 40 664.0625 b010 NRZ
50GE 50GAUI-2 (KP4 FEC) Wide 26.5625 80 332.0312 b110 NRZ
50GE LAUI-2 Consortium Narrow 25.78125 40 644.5313 b010 NRZ
50GE LAUI-2 Consortium Wide 25.78125 80 322.2656 b110 NRZ
50GE 50LAUI-1 Narrow 51.5625 80 644.531 b011 PAM4
50GE 50GAUI-1 (KP4 FEC) Narrow 53.125 80 664.0625 b011 PAM4
50GE 50GAUI-1 Wide 53.125 160 664.0625 b110 PAM4
100GE CAUI-4 Narrow 25.78125 40 644.5313 b010 NRZ
100GE CAUI-4 Wide 25.78125 80 322.2656 b110 NRZ
100GE CAUI-4 (Overclocking) Wide 28.21 80 352.625 b110 NRZ
100GE 100GAUI-4 (KP4 FEC) Narrow 26.5625 40 664.0625 b010 NRZ
100GE 100GAUI-4 (KP4 FEC) Wide 26.5625 80 332.0312 b110 NRZ
100GE 100GAUI-2 (KP4 FEC) Narrow 53.125 80 664.0625 b011 PAM4
100GE 100GAUI-2 Wide 53.125 160 332.03125 b110 PAM4
100GE 100GAUI-2 (Overclocking) 56.42 160 352.625 b110 PAM4
100GE CAUI-2 Narrow 51.5625 80 644.531 b011 PAM4
100GE 100GAUI-1 Narrow 106.25 160 664.0625 b010 PAM4
100GE 100GAUI-1 Wide 106.25 160 332.03125 b110 PAM4
FC32 Single Lane 28.05 80 350.625 b110 NRZ
  1. All the MRMAC 160-bit and 320-bit presets are operating in GAUI-4/CAUI-4 (80-bit) mode and using an external interleaving logic, for the required operation (160/320 bit). Therefore, the ctl_serdes_width setting value for these configs is the same as the CAUI-4/GAUI-4 value.
  2. 10G/40G narrow (16-bit) mode cannot be used with GTM because GTM only supports a minimum data width of 32 bits.