Typical Flex I/F TX and RX transactions can be seen in the following diagrams.
In this example, data transfer into the Flex I/F port is active on Client 0. The user logic
drives data (tx_flex_data1 and tx_flex_data2) into the
interface while asserting tx_flex_ena_0.
Note the relationship between the per-port tx_flex_stall_<N> signal and tx_flex_ena_<N>. The stall signal is output to backpressure the transfers into
the Flex I/F. The interface requires that you suspend transfers (tx_flex_enain == 0) exactly one cycle after the tx_flex_stall_<N> is asserted to 1.
Note: When the flexif interface is configured for OTN mode
(
ctl_tx_flexif_select = 3'b000), the internal scrambler is disabled, and AMs
are passed through but need to be identified. The user logic is responsible for inserting
alignment markers. When an alignment marker is inserted, the user logic must assert
tx_flex_alignmarker<N> to indicate that the data includes an AM. This
prevents the scrambler from scrambling the alignment markers. However, other modes do not use
tx_flex_alignmarker<N>.Figure 1. TX Flex Interface
In the receive direction, the Flex I/F outputs data at the configured port
rate. Valid data is indicated by the per-port signal
rx_flex_ena_<N>. When rx_flex_ena_<N> is
deasserted, the data is invalid. Note: There is no
backpressure from the user logic back to the Flex I/F port. The user logic should be able to
keep up with the selected data rate.
Figure 2. RX Flex Interface
