Examples - 2.3 English

Versal Devices Integrated 100G Multirate Ethernet MAC Subsystem Product Guide (PG314)

Document ID
PG314
Release Date
2024-05-30
Version
2.3 English

The following shows timing diagram examples for the timer adjustments.

System Timer Overwrite

To overwrite the system timer, assert ctl_tx/rx_ptp_st_overwrite_N and drive the desired 54-bit value onto the input signal ctl_tx/rx_ptp_systemtimer_N. The overwrite is triggered by toggling the signal ctl_tx/rx_ptp_st_sync_N.

Figure 1. Timer Overwrite
Note: The ctl_tx/rx_ptp_systemtimer_N and ctl_tx/rx_ptp_st_sync_N signals come from a clock domain that is asynchronous to the timer's clock domain, hence some small delays for retiming.

As mentioned earlier, if the ctl_tx/rx_ptp_st_sync_N transition is sampled to the falling edge of the timer’s clock, a DDR phase compensator automatically adds half a clock period (that is, timer_increment / 2) to the system timer to help improve timer resolution.

Timer Frequency Set Coarse Adjustment

In this example, the system_timer frequency is set by providing a coarse adjustment to the timer_increment.

Figure 2. System Timer – Set Increment Value
Note: The 32-bit ctl_ptp_st_adjust value is interpreted as being in units of 2-8 ns, which means it is mapped into the coarse portion of the increment_value. The sub-nanosecond portion of the increment_value is set to 32’d0. To adjust the sub-nanosecond portion of the increment value, use the Timer Frequency Adjust method.

Timer Frequency Adjust Fine Adjustment

Here is an example of fine-tuning the system_timer frequency by adjusting the sub-nanosecond portion of the increment value (Method 3 on the Adjustment interface). The adjustment is specified to be in units of 2-40 ns. The provided signed adjustment value is added to the existing increment_value and used moving forward.

Figure 3. Fine Frequency Adjust

In this example, a signed adjustment value of 32’hBA9D_1F60 is provided. Because this adjustment value is negative, it results in a subtraction of 42’h4562_E0A0, reducing the increment value from 42’h18D_8AC5_C140 to 42’h18D_4562_E0A0.

Phase Shift

In this diagram, a phase shift to the timer value is shown (Method 1 using the Adjustment interface).

Figure 4. Phase Adjustment
Note: The increment_value only changes for one system_timer iteration (it is a one-shot adjustment) then returns to its previous value. The maximum allowable adjustment is 18’h3_FFFF in units of 2-8 ns.