The following figures show the MRMAC example design with GT Wizard Subsystem (gtwiz_versal IP). In the block diagram, the MRMAC and gtwiz_versal IPs are connected along with the MBUFG_GTs. MRMAC, gtwiz_versal, and MBUFG_GTs are integrated through RTL instantiation in the example design.
For more information on the gtwiz_versal IP, see the Versal Adaptive SoC Transceiver Subsystem Product Guide (PG442).
As shown in the following figure, the MRMAC example design simulation uses a packet generator and monitor to generate and check Ethernet traffic. A test bench controls and monitors the packet generator and also configures the MRMAC IP through an AXI4-Lite interface.
For Implementation, as shown in the subsequent figure, CIPS triggers the generator and monitor and configures the MRMAC IP through the AXI4-Lite interface. The IP folder provides a sample C- Code. Both simulation and validation of the example design starts with GT rate configuration followed by reset. Then the core is configured through the AXI4-Lite interface. This is followed by a loop-back test using the generator and monitor blocks in example design. Finally, it reads the MRMAC statistics to compare the results of RX with TX.
When generating the IP, disable the Use Legacy GT Wizard in Example Design option in the MRMAC IP configuration tab to enable the GT Wizard Subsystem (gtwiz_versal IP) in the example design.
