Example Design Hierarchy - 2.3 English

Versal Devices Integrated 100G Multirate Ethernet MAC Subsystem Product Guide (PG314)

Document ID
PG314
Release Date
2024-05-30
Version
2.3 English

The following figure shows the MRMAC example design. In the block design, the MRMAC and GT Quad Base IP are connected along with the BUFG_GTs. For more information on the GT Quad Base IP, see the Versal Adaptive SoC Transceivers Wizard LogiCORE IP Product Guide (PG331) .

As shown in the following figure, the MRMAC example design simulation uses a packet generator and monitor to generate and check ethernet traffic. A test bench is used to control and monitor the packet generator and also to configure the MRMAC IP through AXI4-Lite interface.

For Implementation, as shown in the subsequent figure, CIPS is used to trigger the generator and monitor and configure the MRMAC IP through the AXI4-Lite interface. A sample C- Code is provided in the IP folder. Both simulation and validation of the example design starts with GT rate configuration followed by reset. Then the core is configured through the AXI4-Lite interface. This is followed by a loop-back test using the generator and monitor blocks in example design. Finally, it reads the MRMAC statistics to compare the results of RX with TX.
Note: For ease of meeting timing in generator and monitors in slow speed devices, the AXIS clock is set to 370 MHz.
Figure 1. MRMAC Example Design (Simulation)

Figure 2. MRMAC Example Design (Implementation)

Note: The MRMAC Tile section in device is currently done by MRMAC GUI ( default set to "X0Y3"). A sample constraint for MRMAC location "X0Y3" is applied to core.xdc (mrmac_0.xdc) file. A suitable GT also suggested in exdes.xdc (mrmac_0_example_top.xdc) file to lock appropriate GT for the selected MRMAC. If you change these locations, you need to take care of the clocking region and routing feasibly.