Example Design Creation, Simulation, and Device Image Generation - 3.1 English - PG314

1. For VCK190 bank 200, for the MRMAC site, select MRMAC X0Y0.
   
   
2. Select the required MRMAC Configuration Type. All the switching presets are present under the Dynamic configuration type and the static presets under the Static Configuration type. For example, if Switching Wide preset is required, select the Dynamic Configuration type.
   
   
3. Select the required GT Wizard. For the legacy GT Wizard, enable Use Legacy GT Wizard in Example Design and disable it for the New GT wizard selection. This option will be deprecated in a future release.
4. Select Switching Wide from the MRMAC Configuration Preset .
   
   
5. Click the GT information tab, select GT refCLK, for example 322.26525, and number of pipeline stages, for example 0. Click OK to finish the IP customization.
   
   

The Vivado project opens with example design ‘mrmac_0’.

Select the Target simulator as required. The Vivado simulator is shown in the following figure.

The example design simulation starts with a core speed of 100GE then does data sanity by sending and receiving few packets in loopback mode. Upon completion, it prints the MRMAC statistics and also the test status. Then, it switches to 50GE, 40GE, 4x25GE, 4x10GE, and repeats the same test.

Once the simulation is successful, you can generate the bitstream for board validation.

For VCK190/VMK180, uncomment the following in the example design .xdc file:

###### Below is the constraints for VCK190 Board(xcvc1902-vsva2197-2MP-e-S-es1) example design MRMAC_X0Y0-GTY Bank 200 .  Uncomment below to use.
##### GTY Bank 200
##set_property PACKAGE_PIN AF2 [get_ports {gt_rxp_in[0]}]
##set_property PACKAGE_PIN AF1 [get_ports {gt_rxn_in[0]}]
##set_property PACKAGE_PIN AF7 [get_ports {gt_txp_out[0]}]
##set_property PACKAGE_PIN AF6 [get_ports {gt_txn_out[0]}]
##set_property PACKAGE_PIN AE4 [get_ports {gt_rxp_in[1]}]
##set_property PACKAGE_PIN AE3 [get_ports {gt_rxn_in[1]}]
##set_property PACKAGE_PIN AE9 [get_ports {gt_txp_out[1]}]
##set_property PACKAGE_PIN AE8 [get_ports {gt_txn_out[1]}]
##set_property PACKAGE_PIN AD2 [get_ports {gt_rxp_in[2]}]
##set_property PACKAGE_PIN AD1 [get_ports {gt_rxn_in[2]}]
##set_property PACKAGE_PIN AD7 [get_ports {gt_txp_out[2]}]
##set_property PACKAGE_PIN AD6 [get_ports {gt_txn_out[2]}]
##set_property PACKAGE_PIN AC4 [get_ports {gt_rxp_in[3]}]
##set_property PACKAGE_PIN AC3 [get_ports {gt_rxn_in[3]}]
##set_property PACKAGE_PIN AC9 [get_ports {gt_txp_out[3]}]
##set_property PACKAGE_PIN AC8 [get_ports {gt_txn_out[3]}]
### GTREFCLK 0 Configured as Output (Recovered Clock) which connects to 8A34001 CLK1_IN
### GTREFCLK 1 ( Driven by 8A34001 Q1 )
##set_property PACKAGE_PIN AD11 [get_ports {gt_ref_clk_p}]
##set_property PACKAGE_PIN AD10 [get_ports {gt_ref_clk_n}]

The Export window opens.