Core Overview - 2.3 English

Versal Devices Integrated 100G Multirate Ethernet MAC Subsystem Product Guide (PG314)

Document ID
PG314
Release Date
2024-05-30
Version
2.3 English

Figure-1 identifies the major functional blocks of the Timer Syncer IP. In this figure only four instances of the port timer are shown for simplicity. The number of port instances are user selectable at the timer of generating core. The core supports up-to 16 instances of port timers.

Figure 1. Timer Syncer IP functional block diagram

The Timer Syncer IP contains all of the functions and interfaces needed to implement a variety of ToD topologies and applications. Further, the IP can be controlled with either SW or HW devices.

The System Timer maintains time on the free-running system time clock (ts_clk) and provides mechanism to synchronize this timer value to the various Port timers, each of which might be clocked on their separate clocks (phy_clk).

To System Timer IP provides timer values in two formats: Timestamp format (or ToD format) is composed of 80 bits containing fields of unsigned positive seconds and nanoseconds as {seconds[47:0], nanoseconds[31:0] }. Correction Field (CF) format which is a signed 64b value in nanoseconds multiplied by 2+16.

The description of the functional blocks and the interfaces are provided in the subsequent sections.